<div dir="ltr"><br><div class="gmail_extra"><br><br><div class="gmail_quote">On Fri, May 16, 2014 at 11:03 AM, akash goel <span dir="ltr"><<a href="mailto:akash.goels@gmail.com" target="_blank">akash.goels@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div> </div><div>Sorry not aware of this specific difference in the starting value of scanline counter for HSW+ (& gen 2), but implementation wise, patch looks fine.</div>
<div> </div><div><div>Reviewed-by: "Akash Goel <<a href="mailto:akash.goels@gmail.com" target="_blank"><font color="#0066cc">akash.goels@gmail.com</font></a>>" </div>
</div></div><div class="HOEnZb"><div class="h5"><div class="gmail_extra"><br></div></div></div></blockquote><div><br></div><div>Don't have enough info about the initial scanline counter values for</div><div>HSW+ and gen2. Otherwise, you can add my r-b tag</div>
<div> </div><div>Reviewed-by: "Sourab Gupta <<a href="mailto:sourabgupta@gmail.com">sourabgupta@gmail.com</a>>" </div><div><br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div class="HOEnZb"><div class="h5"><div class="gmail_extra"><span style="color:rgb(34,34,34)"> </span><br></div></div></div></blockquote><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div class="HOEnZb"><div class="h5"><div class="gmail_extra"><div class="gmail_quote">On Thu, May 15, 2014 at 10:53 PM, <span dir="ltr"><<a href="mailto:ville.syrjala@linux.intel.com" target="_blank">ville.syrjala@linux.intel.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">From: Ville Syrjälä <<a href="mailto:ville.syrjala@linux.intel.com" target="_blank">ville.syrjala@linux.intel.com</a>><br>
<br>
On gen2 the scanline counter behaves a bit differently from the<br>
later generations. Instead of adding one to the raw scanline<br>
counter value, we must subtract one.<br>
<br>
On HSW/BDW the scanline counter requires a +2 adjustment on HDMI<br>
outputs. DP outputs on the on the other require the typical +1<br>
adjustment.<br>
<br>
As the fixup we must apply to the hardware scanline counter<br>
depends on several factors, compute the desired offset at modeset<br>
time and tuck it away for when it's needed.<br>
<br>
v2: Clarify HSW+ situation<br>
<br>
Signed-off-by: Ville Syrjälä <<a href="mailto:ville.syrjala@linux.intel.com" target="_blank">ville.syrjala@linux.intel.com</a>><br>
---<br>
drivers/gpu/drm/i915/i915_irq.c | 14 ++++-------<br>
drivers/gpu/drm/i915/intel_display.c | 45 +++++++++++++++++++++++++++++++++++-<br>
drivers/gpu/drm/i915/intel_drv.h | 2 ++<br>
3 files changed, 51 insertions(+), 10 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c<br>
index bb9b061..80003b5 100644<br>
--- a/drivers/gpu/drm/i915/i915_irq.c<br>
+++ b/drivers/gpu/drm/i915/i915_irq.c<br>
@@ -818,9 +818,9 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)<br>
struct drm_i915_private *dev_priv = dev->dev_private;<br>
const struct drm_display_mode *mode = &crtc->config.adjusted_mode;<br>
enum pipe pipe = crtc->pipe;<br>
- int vtotal = mode->crtc_vtotal;<br>
- int position;<br>
+ int position, vtotal;<br>
<br>
+ vtotal = mode->crtc_vtotal;<br>
if (mode->flags & DRM_MODE_FLAG_INTERLACE)<br>
vtotal /= 2;<br>
<br>
@@ -830,14 +830,10 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)<br>
position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;<br>
<br>
/*<br>
- * Scanline counter increments at leading edge of hsync, and<br>
- * it starts counting from vtotal-1 on the first active line.<br>
- * That means the scanline counter value is always one less<br>
- * than what we would expect. Ie. just after start of vblank,<br>
- * which also occurs at start of hsync (on the last active line),<br>
- * the scanline counter will read vblank_start-1.<br>
+ * See update_scanline_offset() for the details on the<br>
+ * scanline_offset adjustment.<br>
*/<br>
- return (position + 1) % vtotal;<br>
+ return (position + crtc->scanline_offset) % vtotal;<br>
}<br>
<br>
static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,<br>
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c<br>
index 0f8f9bc..f7222d7 100644<br>
--- a/drivers/gpu/drm/i915/intel_display.c<br>
+++ b/drivers/gpu/drm/i915/intel_display.c<br>
@@ -10164,6 +10164,44 @@ void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config<br>
pipe_config->adjusted_mode.crtc_clock, dotclock);<br>
}<br>
<br>
+static void update_scanline_offset(struct intel_crtc *crtc)<br>
+{<br>
+ struct drm_device *dev = crtc->base.dev;<br>
+<br>
+ /*<br>
+ * The scanline counter increments at the leading edge of hsync.<br>
+ *<br>
+ * On most platforms it starts counting from vtotal-1 on the<br>
+ * first active line. That means the scanline counter value is<br>
+ * always one less than what we would expect. Ie. just after<br>
+ * start of vblank, which also occurs at start of hsync (on the<br>
+ * last active line), the scanline counter will read vblank_start-1.<br>
+ *<br>
+ * On gen2 the scanline counter starts counting from 1 instead<br>
+ * of vtotal-1, so we have to subtract one (or rather add vtotal-1<br>
+ * to keep the value positive), instead of adding one.<br>
+ *<br>
+ * On HSW+ the behaviour of the scanline counter depends on the output<br>
+ * type. For DP ports it behaves like most other platforms, but on HDMI<br>
+ * there's an extra 1 line difference. So we need to add two instead of<br>
+ * one to the value.<br>
+ */<br>
+ if (IS_GEN2(dev)) {<br>
+ const struct drm_display_mode *mode = &crtc->config.adjusted_mode;<br>
+ int vtotal;<br>
+<br>
+ vtotal = mode->crtc_vtotal;<br>
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE)<br>
+ vtotal /= 2;<br>
+<br>
+ crtc->scanline_offset = vtotal - 1;<br>
+ } else if (HAS_DDI(dev) &&<br>
+ intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {<br>
+ crtc->scanline_offset = 2;<br>
+ } else<br>
+ crtc->scanline_offset = 1;<br>
+}<br>
+<br>
static int __intel_set_mode(struct drm_crtc *crtc,<br>
struct drm_display_mode *mode,<br>
int x, int y, struct drm_framebuffer *fb)<br>
@@ -10262,8 +10300,11 @@ static int __intel_set_mode(struct drm_crtc *crtc,<br>
}<br>
<br>
/* Now enable the clocks, plane, pipe, and connectors that we set up. */<br>
- for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)<br>
+ for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {<br>
+ update_scanline_offset(intel_crtc);<br>
+<br>
dev_priv->display.crtc_enable(&intel_crtc->base);<br>
+ }<br>
<br>
/* FIXME: add subpixel order */<br>
done:<br>
@@ -11789,6 +11830,8 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)<br>
*/<br>
crtc->cpu_fifo_underrun_disabled = true;<br>
crtc->pch_fifo_underrun_disabled = true;<br>
+<br>
+ update_scanline_offset(crtc);<br>
}<br>
}<br>
<br>
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h<br>
index 32a74e1..dd562b9 100644<br>
--- a/drivers/gpu/drm/i915/intel_drv.h<br>
+++ b/drivers/gpu/drm/i915/intel_drv.h<br>
@@ -403,6 +403,8 @@ struct intel_crtc {<br>
} wm;<br>
<br>
wait_queue_head_t vbl_wait;<br>
+<br>
+ int scanline_offset;<br>
};<br>
<br>
struct intel_plane_wm_parameters {<br>
<span><font color="#888888">--<br>
1.8.3.2<br>
<br>
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