<div dir="ltr"><div class="gmail_extra"><br><br><div class="gmail_quote">On Thu, May 15, 2014 at 10:50 PM, <span dir="ltr"><<a href="mailto:ville.syrjala@linux.intel.com" target="_blank">ville.syrjala@linux.intel.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="">From: Ville Syrjälä <<a href="mailto:ville.syrjala@linux.intel.com">ville.syrjala@linux.intel.com</a>><br>
<br>
The docs are a bit lacking when it comes to describing when certain<br>
timing related events occur in the hardware. Draw a picture which<br>
tries to capture the most important ones.<br>
<br>
v2: Clarify a few details (Imre)<br>
</div>v3: Add HSW+ HDMI scanline counter numbers<br>
<br>
Acked-by: Imre Deak <<a href="mailto:imre.deak@intel.com">imre.deak@intel.com</a>><br>
Reviewed-by: Akash Goel <<a href="mailto:akash.goels@gmail.com">akash.goels@gmail.com</a>><br>
<div class="">Signed-off-by: Ville Syrjälä <<a href="mailto:ville.syrjala@linux.intel.com">ville.syrjala@linux.intel.com</a>><br>
---<br>
</div> drivers/gpu/drm/i915/i915_irq.c | 50 +++++++++++++++++++++++++++++++++++++++++<br>
1 file changed, 50 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c<br>
index bdb0b67..bb9b061 100644<br>
--- a/drivers/gpu/drm/i915/i915_irq.c<br>
+++ b/drivers/gpu/drm/i915/i915_irq.c<br>
@@ -669,6 +669,56 @@ i915_pipe_enabled(struct drm_device *dev, int pipe)<br>
<div class=""> }<br>
}<br>
<br>
+/*<br>
+ * This timing diagram depicts the video signal in and<br>
+ * around the vertical blanking period.<br>
+ *<br>
+ * Assumptions about the fictitious mode used in this example:<br>
+ * vblank_start >= 3<br>
+ * vsync_start = vblank_start + 1<br>
+ * vsync_end = vblank_start + 2<br>
+ * vtotal = vblank_start + 3<br>
+ *<br>
+ * start of vblank:<br>
+ * latch double buffered registers<br>
+ * increment frame counter (ctg+)<br>
+ * generate start of vblank interrupt (gen4+)<br>
+ * |<br>
+ * | frame start:<br>
+ * | generate frame start interrupt (aka. vblank interrupt) (gmch)<br>
+ * | may be shifted forward 1-3 extra lines via PIPECONF<br>
+ * | |<br>
+ * | | start of vsync:<br>
+ * | | generate vsync interrupt<br>
+ * | | |<br>
</div>+ * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx<br>
<div class="">+ * . \hs/ . \hs/ \hs/ \hs/ . \hs/<br>
</div>+ * ----va---> <-----------------vb--------------------> <--------va-------------<br>
+ * | | <----vs-----> |<br>
+ * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)<br>
+ * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)<br>
+ * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)<br>
<div class="HOEnZb"><div class="h5">+ * | | |<br>
+ * last visible pixel first visible pixel<br>
+ * | increment frame counter (gen3/4)<br>
+ * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)<br>
+ *<br>
+ * x = horizontal active<br>
+ * _ = horizontal blanking<br>
+ * hs = horizontal sync<br>
+ * va = vertical active<br>
+ * vb = vertical blanking<br>
+ * vs = vertical sync<br>
+ * vbs = vblank_start (number)<br>
+ *<br>
+ * Summary:<br>
+ * - most events happen at the start of horizontal sync<br>
+ * - frame start happens at the start of horizontal blank, 1-4 lines<br>
+ * (depending on PIPECONF settings) after the start of vblank<br>
+ * - gen3/4 pixel and frame counter are synchronized with the start<br>
+ * of horizontal active on the first line of vertical active<br>
+ */<br>
+<br>
static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)<br>
{<br>
/* Gen2 doesn't have a hardware frame counter */<br>
--<br>
1.8.3.2<br>
<br></div></div></blockquote><div> </div><div>I'm not really sure how the scanline counter moves in the HSW and HDMI case.</div><div>Other than that, you can add my r-b tag:</div><div>Reviewed-by: "Sourab Gupta <<a href="mailto:sourabgupta@gmail.com">sourabgupta@gmail.com</a>>"</div>
<div><br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="HOEnZb"><div class="h5">
_______________________________________________<br>
Intel-gfx mailing list<br>
<a href="mailto:Intel-gfx@lists.freedesktop.org">Intel-gfx@lists.freedesktop.org</a><br>
<a href="http://lists.freedesktop.org/mailman/listinfo/intel-gfx" target="_blank">http://lists.freedesktop.org/mailman/listinfo/intel-gfx</a><br>
</div></div></blockquote></div><br></div></div>