<div dir="ltr">It seems it needs a rebase...<div>I couldn't figure out where exactly you will put the wait_for_pending so I'm going to wait a v2.</div><div><br></div><div>But this is my fault that took a century to review it... I'm sorry...</div>
</div><div class="gmail_extra"><br><br><div class="gmail_quote">On Tue, Apr 15, 2014 at 11:41 AM, <span dir="ltr"><<a href="mailto:ville.syrjala@linux.intel.com" target="_blank">ville.syrjala@linux.intel.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">From: Ville Syrjälä <<a href="mailto:ville.syrjala@linux.intel.com">ville.syrjala@linux.intel.com</a>><br>
<br>
We have to write to the primary plane base address registrer when we<br>
enable/disable the primary plane in response to sprite coverage. Those<br>
writes will cause the flip counter to increment which could interfere<br>
with the detection of CS flip completion. We could end up completing<br>
CS flips before the CS has even executed the commands from the ring.<br>
<br>
To avoid such issues, wait for CS flips to finish before we toggle the<br>
primary plane on/off.<br>
<br>
Testcase: igt/kms_mmio_vs_cs_flip/setplane_vs_cs_flip<br>
Signed-off-by: Ville Syrjälä <<a href="mailto:ville.syrjala@linux.intel.com">ville.syrjala@linux.intel.com</a>><br>
---<br>
drivers/gpu/drm/i915/intel_display.c | 2 +-<br>
drivers/gpu/drm/i915/intel_drv.h | 1 +<br>
drivers/gpu/drm/i915/intel_sprite.c | 4 ++++<br>
3 files changed, 6 insertions(+), 1 deletion(-)<br>
<br>
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c<br>
index 9b181fc..c0fe5dd 100644<br>
--- a/drivers/gpu/drm/i915/intel_display.c<br>
+++ b/drivers/gpu/drm/i915/intel_display.c<br>
@@ -3096,7 +3096,7 @@ bool intel_has_pending_fb_unpin(struct drm_device *dev)<br>
return false;<br>
}<br>
<br>
-static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)<br>
+void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)<br>
{<br>
struct drm_device *dev = crtc->dev;<br>
struct drm_i915_private *dev_priv = dev->dev_private;<br>
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h<br>
index edef34e..f578e42 100644<br>
--- a/drivers/gpu/drm/i915/intel_drv.h<br>
+++ b/drivers/gpu/drm/i915/intel_drv.h<br>
@@ -775,6 +775,7 @@ int valleyview_get_vco(struct drm_i915_private *dev_priv);<br>
void intel_mode_from_pipe_config(struct drm_display_mode *mode,<br>
struct intel_crtc_config *pipe_config);<br>
int intel_format_to_fourcc(int format);<br>
+void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);<br>
<br>
/* intel_dp.c */<br>
void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);<br>
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c<br>
index 4df7245..36a8f5e 100644<br>
--- a/drivers/gpu/drm/i915/intel_sprite.c<br>
+++ b/drivers/gpu/drm/i915/intel_sprite.c<br>
@@ -529,6 +529,8 @@ intel_enable_primary(struct drm_crtc *crtc)<br>
if (intel_crtc->primary_enabled)<br>
return;<br>
<br>
+ intel_crtc_wait_for_pending_flips(crtc);<br>
+<br>
intel_crtc->primary_enabled = true;<br>
<br>
I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);<br>
@@ -558,6 +560,8 @@ intel_disable_primary(struct drm_crtc *crtc)<br>
if (!intel_crtc->primary_enabled)<br>
return;<br>
<br>
+ intel_crtc_wait_for_pending_flips(crtc);<br>
+<br>
intel_crtc->primary_enabled = false;<br>
<br>
mutex_lock(&dev->struct_mutex);<br>
<span class="HOEnZb"><font color="#888888">--<br>
1.8.3.2<br>
<br>
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</font></span></blockquote></div><br><br clear="all"><div><br></div>-- <br><div>Rodrigo Vivi</div><div>Blog: <a href="http://blog.vivi.eng.br" target="_blank">http://blog.vivi.eng.br</a></div><div> </div>
</div>