<div dir="ltr"><div>Reviewed-by: Rodrigo Vivi <<a href="mailto:rodrigo.vivi@gmail.com">rodrigo.vivi@gmail.com</a>><br></div></div><div class="gmail_extra"><br><br><div class="gmail_quote">On Fri, Apr 25, 2014 at 3:30 AM, <span dir="ltr"><<a href="mailto:ville.syrjala@linux.intel.com" target="_blank">ville.syrjala@linux.intel.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="">From: Ville Syrjälä <<a href="mailto:ville.syrjala@linux.intel.com">ville.syrjala@linux.intel.com</a>><br>
<br>
Now that we've plugged the mmio vs. ring flip race, we shouldn't need<br>
these vblank waits in the modeset codepaths anymore. So get rid of<br>
them.<br>
<br>
</div>v2: gen2 needs to wait for planes to turn off before disabling pipe<br>
<div class=""><br>
Signed-off-by: Ville Syrjälä <<a href="mailto:ville.syrjala@linux.intel.com">ville.syrjala@linux.intel.com</a>><br>
---<br>
</div> drivers/gpu/drm/i915/intel_display.c | 19 +++++++------------<br>
1 file changed, 7 insertions(+), 12 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c<br>
index 33d21bf..17258fe5 100644<br>
<div><div class="h5">--- a/drivers/gpu/drm/i915/intel_display.c<br>
+++ b/drivers/gpu/drm/i915/intel_display.c<br>
@@ -1901,7 +1901,6 @@ static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,<br>
<br>
I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);<br>
intel_flush_primary_plane(dev_priv, plane);<br>
- intel_wait_for_vblank(dev_priv->dev, pipe);<br>
}<br>
<br>
/**<br>
@@ -1931,7 +1930,6 @@ static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,<br>
<br>
I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);<br>
intel_flush_primary_plane(dev_priv, plane);<br>
- intel_wait_for_vblank(dev_priv->dev, pipe);<br>
}<br>
<br>
static bool need_vtd_wa(struct drm_device *dev)<br>
@@ -3706,16 +3704,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)<br>
if (HAS_PCH_CPT(dev))<br>
cpt_verify_modeset(dev, intel_crtc->pipe);<br>
<br>
- /*<br>
- * There seems to be a race in PCH platform hw (at least on some<br>
- * outputs) where an enabled pipe still completes any pageflip right<br>
- * away (as if the pipe is off) instead of waiting for vblank. As soon<br>
- * as the first vblank happend, everything works as expected. Hence just<br>
- * wait for one vblank before returning to avoid strange things<br>
- * happening.<br>
- */<br>
- intel_wait_for_vblank(dev, intel_crtc->pipe);<br>
-<br>
drm_vblank_on(dev, pipe);<br>
}<br>
<br>
</div></div>@@ -4475,6 +4463,13 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)<br>
intel_disable_planes(crtc);<br>
intel_disable_primary_hw_plane(dev_priv, plane, pipe);<br>
<br>
+ /*<br>
+ * On gen2 planes are double buffered but the pipe isn't, so we must<br>
+ * wait for planes to fully turn off before disabling the pipe.<br>
+ */<br>
+ if (IS_GEN2(dev))<br>
+ intel_wait_for_vblank(dev, pipe);<br>
+<br>
intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);<br>
intel_disable_pipe(dev_priv, pipe);<br>
<div class="HOEnZb"><div class="h5"><br>
--<br>
1.8.3.2<br>
<br>
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</div></div></blockquote></div><br><br clear="all"><div><br></div>-- <br><div>Rodrigo Vivi</div><div>Blog: <a href="http://blog.vivi.eng.br" target="_blank">http://blog.vivi.eng.br</a></div><div> </div>
</div>