<div dir="ltr">Reviewed-by Rodrigo Vivi <<a href="mailto:rodrigo.vivi@gmail.com">rodrigo.vivi@gmail.com</a>></div><div class="gmail_extra"><br><br><div class="gmail_quote">On Wed, May 21, 2014 at 4:04 AM,  <span dir="ltr"><<a href="mailto:ville.syrjala@linux.intel.com" target="_blank">ville.syrjala@linux.intel.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="">From: Ville Syrjälä <<a href="mailto:ville.syrjala@linux.intel.com">ville.syrjala@linux.intel.com</a>><br>

<br>
We have to write to the primary plane base address registrer when we<br>
enable/disable the primary plane in response to sprite coverage. Those<br>
writes will cause the flip counter to increment which could interfere<br>
with the detection of CS flip completion. We could end up completing<br>
CS flips before the CS has even executed the commands from the ring.<br>
<br>
To avoid such issues, wait for CS flips to finish before we toggle the<br>
primary plane on/off.<br>
<br>
</div>v2: Rebased due to atomic sprite update changes<br>
<div class=""><br>
Testcase: igt/kms_mmio_vs_cs_flip/setplane_vs_cs_flip<br>
Signed-off-by: Ville Syrjälä <<a href="mailto:ville.syrjala@linux.intel.com">ville.syrjala@linux.intel.com</a>><br>
---<br>
 drivers/gpu/drm/i915/intel_display.c | 2 +-<br>
</div> drivers/gpu/drm/i915/intel_drv.h     | 2 ++<br>
 drivers/gpu/drm/i915/intel_sprite.c  | 3 +++<br>
<div class=""> 3 files changed, 6 insertions(+), 1 deletion(-)<br>
<br>
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c<br>
</div>index 8ca8b2f..849bc71 100644<br>
--- a/drivers/gpu/drm/i915/intel_display.c<br>
+++ b/drivers/gpu/drm/i915/intel_display.c<br>
@@ -3291,7 +3291,7 @@ bool intel_has_pending_fb_unpin(struct drm_device *dev)<br>
<div class="">        return false;<br>
 }<br>
<br>
-static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)<br>
+void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)<br>
 {<br>
        struct drm_device *dev = crtc->dev;<br>
        struct drm_i915_private *dev_priv = dev->dev_private;<br>
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h<br>
</div>index a78eb75..b9b13eb 100644<br>
--- a/drivers/gpu/drm/i915/intel_drv.h<br>
+++ b/drivers/gpu/drm/i915/intel_drv.h<br>
@@ -801,6 +801,8 @@ int valleyview_get_vco(struct drm_i915_private *dev_priv);<br>
<div class=""> void intel_mode_from_pipe_config(struct drm_display_mode *mode,<br>
                                 struct intel_crtc_config *pipe_config);<br>
 int intel_format_to_fourcc(int format);<br>
+void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);<br>
+<br>
<br>
 /* intel_dp.c */<br>
 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);<br>
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c<br>
</div>index 7780f6c..d6acd6b 100644<br>
--- a/drivers/gpu/drm/i915/intel_sprite.c<br>
+++ b/drivers/gpu/drm/i915/intel_sprite.c<br>
@@ -1018,6 +1018,9 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,<br>
<br>
                intel_crtc->primary_enabled = primary_enabled;<br>
<br>
+               if (primary_was_enabled != primary_enabled)<br>
+                       intel_crtc_wait_for_pending_flips(crtc);<br>
+<br>
                if (primary_was_enabled && !primary_enabled)<br>
                        intel_pre_disable_primary(crtc);<br>
<span class="HOEnZb"><font color="#888888"><br>
--<br>
1.8.5.5<br>
</font></span><div class="HOEnZb"><div class="h5"><br>
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</div></div></blockquote></div><br><br clear="all"><div><br></div>-- <br><div>Rodrigo Vivi</div><div>Blog: <a href="http://blog.vivi.eng.br" target="_blank">http://blog.vivi.eng.br</a></div><div> </div>
</div>