<div dir="ltr"><div>Reviewed-by: Rodrigo Vivi <<a href="mailto:rodrigo.vivi@intel.com">rodrigo.vivi@intel.com</a>><br></div></div><div class="gmail_extra"><br><br><div class="gmail_quote">On Fri, Jul 4, 2014 at 7:50 AM, Paulo Zanoni <span dir="ltr"><<a href="mailto:przanoni@gmail.com" target="_blank">przanoni@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">From: Paulo Zanoni <<a href="mailto:paulo.r.zanoni@intel.com">paulo.r.zanoni@intel.com</a>><br>
<br>
Move it from hsw_power_well_post_enable() (intel_pm.c) to i915_irq.c<br>
so we can reuse the nice IRQ macros we have there. The main difference<br>
is that now we're going to check if the IIR register is non-zero when<br>
we try to re-enable the interrupts.<br>
<br>
Signed-off-by: Paulo Zanoni <<a href="mailto:paulo.r.zanoni@intel.com">paulo.r.zanoni@intel.com</a>><br>
---<br>
 drivers/gpu/drm/i915/i915_irq.c  | 12 ++++++++++++<br>
 drivers/gpu/drm/i915/intel_drv.h |  1 +<br>
 drivers/gpu/drm/i915/intel_pm.c  | 18 ++----------------<br>
 3 files changed, 15 insertions(+), 16 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c<br>
index 2e116e9d..a8b8b6b 100644<br>
--- a/drivers/gpu/drm/i915/i915_irq.c<br>
+++ b/drivers/gpu/drm/i915/i915_irq.c<br>
@@ -3204,6 +3204,18 @@ static void gen8_irq_reset(struct drm_device *dev)<br>
        ibx_irq_reset(dev);<br>
 }<br>
<br>
+void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)<br>
+{<br>
+       unsigned long irqflags;<br>
+<br>
+       spin_lock_irqsave(&dev_priv->irq_lock, irqflags);<br>
+       GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],<br>
+                         ~dev_priv->de_irq_mask[PIPE_B]);<br>
+       GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],<br>
+                         ~dev_priv->de_irq_mask[PIPE_C]);<br>
+       spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);<br>
+}<br>
+<br>
 static void cherryview_irq_preinstall(struct drm_device *dev)<br>
 {<br>
        struct drm_i915_private *dev_priv = dev->dev_private;<br>
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h<br>
index 5f7c7bd..46a3a09 100644<br>
--- a/drivers/gpu/drm/i915/intel_drv.h<br>
+++ b/drivers/gpu/drm/i915/intel_drv.h<br>
@@ -687,6 +687,7 @@ void intel_runtime_pm_disable_interrupts(struct drm_device *dev);<br>
 void intel_runtime_pm_restore_interrupts(struct drm_device *dev);<br>
 int intel_get_crtc_scanline(struct intel_crtc *crtc);<br>
 void i9xx_check_fifo_underruns(struct drm_device *dev);<br>
+void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);<br>
<br>
<br>
 /* intel_crt.c */<br>
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c<br>
index 31ae2b4..4cc9e5c 100644<br>
--- a/drivers/gpu/drm/i915/intel_pm.c<br>
+++ b/drivers/gpu/drm/i915/intel_pm.c<br>
@@ -5913,7 +5913,6 @@ bool intel_display_power_enabled(struct drm_i915_private *dev_priv,<br>
 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)<br>
 {<br>
        struct drm_device *dev = dev_priv->dev;<br>
-       unsigned long irqflags;<br>
<br>
        /*<br>
         * After we re-enable the power well, if we touch VGA register 0x3d5<br>
@@ -5929,21 +5928,8 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)<br>
        outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);<br>
        vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);<br>
<br>
-       if (IS_BROADWELL(dev)) {<br>
-               spin_lock_irqsave(&dev_priv->irq_lock, irqflags);<br>
-               I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),<br>
-                          dev_priv->de_irq_mask[PIPE_B]);<br>
-               I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),<br>
-                          ~dev_priv->de_irq_mask[PIPE_B] |<br>
-                          GEN8_PIPE_VBLANK);<br>
-               I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),<br>
-                          dev_priv->de_irq_mask[PIPE_C]);<br>
-               I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),<br>
-                          ~dev_priv->de_irq_mask[PIPE_C] |<br>
-                          GEN8_PIPE_VBLANK);<br>
-               POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));<br>
-               spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);<br>
-       }<br>
+       if (IS_BROADWELL(dev))<br>
+               gen8_irq_power_well_post_enable(dev_priv);<br>
 }<br>
<br>
 static void hsw_set_power_well(struct drm_i915_private *dev_priv,<br>
<span class="HOEnZb"><font color="#888888">--<br>
2.0.0<br>
<br>
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</font></span></blockquote></div><br><br clear="all"><div><br></div>-- <br><div>Rodrigo Vivi</div><div>Blog: <a href="http://blog.vivi.eng.br" target="_blank">http://blog.vivi.eng.br</a></div><div> </div>
</div>