<div dir="ltr"><br><div class="gmail_extra"><br><br><div class="gmail_quote">On Fri, Aug 1, 2014 at 2:14 PM, Paulo Zanoni <span dir="ltr"><<a href="mailto:przanoni@gmail.com" target="_blank">przanoni@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">From: Paulo Zanoni <<a href="mailto:paulo.r.zanoni@intel.com">paulo.r.zanoni@intel.com</a>><br>
<br>
The GEN6_PM* registers don't exist on BDW anymore, so when we read<br>
this file we trigger unclaimed register errors. The equivalent BDW<br>
register for PMs is GEN8_GT_I*R(2), so use it.<br>
<br>
Testcase: igt/pm_rpm/debugfs-read<br>
Signed-off-by: Paulo Zanoni <<a href="mailto:paulo.r.zanoni@intel.com">paulo.r.zanoni@intel.com</a>><br>
---<br>
drivers/gpu/drm/i915/i915_debugfs.c | 20 +++++++++++++++-----<br>
1 file changed, 15 insertions(+), 5 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c<br>
index 9e737b7..17bd20ff 100644<br>
--- a/drivers/gpu/drm/i915/i915_debugfs.c<br>
+++ b/drivers/gpu/drm/i915/i915_debugfs.c<br>
@@ -1024,6 +1024,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)<br>
u32 rpstat, cagf, reqf;<br>
u32 rpupei, rpcurup, rpprevup;<br>
u32 rpdownei, rpcurdown, rpprevdown;<br>
+ u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;<br>
int max_freq;<br>
<br>
/* RPSTAT1 is in the GT power well */<br>
@@ -1061,12 +1062,21 @@ static int i915_frequency_info(struct seq_file *m, void *unused)<br>
gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);<br>
mutex_unlock(&dev->struct_mutex);<br>
<br>
+ if (IS_GEN6(dev) || IS_GEN7(dev)) {<br>
+ pm_ier = I915_READ(GEN6_PMIER);<br>
+ pm_imr = I915_READ(GEN6_PMIMR);<br>
+ pm_isr = I915_READ(GEN6_PMISR);<br>
+ pm_iir = I915_READ(GEN6_PMIIR);<br>
+ pm_mask = I915_READ(GEN6_PMINTRMSK);<br>
+ } else {<br>
+ pm_ier = I915_READ(GEN8_GT_IER(2));<br>
+ pm_imr = I915_READ(GEN8_GT_IMR(2));<br>
+ pm_isr = I915_READ(GEN8_GT_ISR(2));<br>
+ pm_iir = I915_READ(GEN8_GT_IIR(2));<br></blockquote><div><br></div><div>Why do we care only about GT(2) interrupt reg?</div><div>What about other 0, 1 and 3 regs?</div><div><br></div><div>Could this explain GT3 failures?</div>
<div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
+ pm_mask = I915_READ(GEN6_PMINTRMSK);<br>
+ }<br>
seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",<br>
- I915_READ(GEN6_PMIER),<br>
- I915_READ(GEN6_PMIMR),<br>
- I915_READ(GEN6_PMISR),<br>
- I915_READ(GEN6_PMIIR),<br>
- I915_READ(GEN6_PMINTRMSK));<br>
+ pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);<br>
seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);<br>
seq_printf(m, "Render p-state ratio: %d\n",<br>
(gt_perf_status & 0xff00) >> 8);<br>
<span class="HOEnZb"><font color="#888888">--<br>
2.0.1<br>
<br>
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</font></span></blockquote></div><br><br clear="all"><div><br></div>-- <br><div>Rodrigo Vivi</div><div>Blog: <a href="http://blog.vivi.eng.br" target="_blank">http://blog.vivi.eng.br</a></div><div> </div>
</div></div>