<div dir="ltr"><br><div class="gmail_extra"><br><br><div class="gmail_quote">On Fri, Aug 15, 2014 at 10:12 AM, Paulo Zanoni <span dir="ltr"><<a href="mailto:przanoni@gmail.com" target="_blank">przanoni@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">2014-08-15 13:50 GMT-03:00 Rodrigo Vivi <<a href="mailto:rodrigo.vivi@gmail.com">rodrigo.vivi@gmail.com</a>>:<br>
<div><div class="h5">><br>
><br>
><br>
> On Fri, Aug 1, 2014 at 2:14 PM, Paulo Zanoni <<a href="mailto:przanoni@gmail.com">przanoni@gmail.com</a>> wrote:<br>
>><br>
>> From: Paulo Zanoni <<a href="mailto:paulo.r.zanoni@intel.com">paulo.r.zanoni@intel.com</a>><br>
>><br>
>> The GEN6_PM* registers don't exist on BDW anymore, so when we read<br>
>> this file we trigger unclaimed register errors. The equivalent BDW<br>
>> register for PMs is GEN8_GT_I*R(2), so use it.<br>
>><br>
>> Testcase: igt/pm_rpm/debugfs-read<br>
>> Signed-off-by: Paulo Zanoni <<a href="mailto:paulo.r.zanoni@intel.com">paulo.r.zanoni@intel.com</a>><br>
>> ---<br>
>> drivers/gpu/drm/i915/i915_debugfs.c | 20 +++++++++++++++-----<br>
>> 1 file changed, 15 insertions(+), 5 deletions(-)<br>
>><br>
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c<br>
>> b/drivers/gpu/drm/i915/i915_debugfs.c<br>
>> index 9e737b7..17bd20ff 100644<br>
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c<br>
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c<br>
>> @@ -1024,6 +1024,7 @@ static int i915_frequency_info(struct seq_file *m,<br>
>> void *unused)<br>
>> u32 rpstat, cagf, reqf;<br>
>> u32 rpupei, rpcurup, rpprevup;<br>
>> u32 rpdownei, rpcurdown, rpprevdown;<br>
>> + u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;<br>
>> int max_freq;<br>
>><br>
>> /* RPSTAT1 is in the GT power well */<br>
>> @@ -1061,12 +1062,21 @@ static int i915_frequency_info(struct seq_file *m,<br>
>> void *unused)<br>
>> gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);<br>
>> mutex_unlock(&dev->struct_mutex);<br>
>><br>
>> + if (IS_GEN6(dev) || IS_GEN7(dev)) {<br>
>> + pm_ier = I915_READ(GEN6_PMIER);<br>
>> + pm_imr = I915_READ(GEN6_PMIMR);<br>
>> + pm_isr = I915_READ(GEN6_PMISR);<br>
>> + pm_iir = I915_READ(GEN6_PMIIR);<br>
>> + pm_mask = I915_READ(GEN6_PMINTRMSK);<br>
>> + } else {<br>
>> + pm_ier = I915_READ(GEN8_GT_IER(2));<br>
>> + pm_imr = I915_READ(GEN8_GT_IMR(2));<br>
>> + pm_isr = I915_READ(GEN8_GT_ISR(2));<br>
>> + pm_iir = I915_READ(GEN8_GT_IIR(2));<br>
><br>
><br>
> Why do we care only about GT(2) interrupt reg?<br>
> What about other 0, 1 and 3 regs?<br>
<br>
</div></div>Because, as far as I could see, the GEN8_GT(2) register is the one<br>
that seems to be equivalent to the old GEN6_PM register in terms of<br>
the functionality debugged by this function: it is the one that<br>
contains all the RPS stuff. Another thing that influenced me to take<br>
this decision was that, for example, snb_update_pm_irq() touches<br>
GEN6_PM, while bdw_update_pm_irq() touches only GEN8_GT(2). But I'm<br>
not a great user of this code, so maybe we do want more interrupts.<br>
OTOH, if we want all, there's always i915_interrupt_info.<br></blockquote><div><br></div><div>Yeah, makes sense.</div><div><br></div><div>Reviewed-by: Rodrigo Vivi <<a href="mailto:rodrigo.vivi@intel.com">rodrigo.vivi@intel.com</a>></div>
<div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
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><br>
> Could this explain GT3 failures?<br>
<br>
</div>Which GT3 failures? I don't understand why you ask this.<br></blockquote><div><br></div><div>forget about the gt3 on this, and thanks for the ideas!</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div class="HOEnZb"><div class="h5"><br>
><br>
>><br>
>> + pm_mask = I915_READ(GEN6_PMINTRMSK);<br>
>> + }<br>
>> seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x<br>
>> IIR=0x%08x, MASK=0x%08x\n",<br>
>> - I915_READ(GEN6_PMIER),<br>
>> - I915_READ(GEN6_PMIMR),<br>
>> - I915_READ(GEN6_PMISR),<br>
>> - I915_READ(GEN6_PMIIR),<br>
>> - I915_READ(GEN6_PMINTRMSK));<br>
>> + pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);<br>
>> seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);<br>
>> seq_printf(m, "Render p-state ratio: %d\n",<br>
>> (gt_perf_status & 0xff00) >> 8);<br>
>> --<br>
>> 2.0.1<br>
>><br>
>> _______________________________________________<br>
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>> <a href="mailto:Intel-gfx@lists.freedesktop.org">Intel-gfx@lists.freedesktop.org</a><br>
>> <a href="http://lists.freedesktop.org/mailman/listinfo/intel-gfx" target="_blank">http://lists.freedesktop.org/mailman/listinfo/intel-gfx</a><br>
><br>
><br>
><br>
><br>
> --<br>
> Rodrigo Vivi<br>
> Blog: <a href="http://blog.vivi.eng.br" target="_blank">http://blog.vivi.eng.br</a><br>
><br>
<br>
<br>
<br>
</div></div><span class="HOEnZb"><font color="#888888">--<br>
Paulo Zanoni<br>
</font></span></blockquote></div><br><br clear="all"><div><br></div>-- <br><div>Rodrigo Vivi</div><div>Blog: <a href="http://blog.vivi.eng.br" target="_blank">http://blog.vivi.eng.br</a></div><div> </div>
</div></div>