<div dir="ltr">Please just ignore my latest comment here...<div>I confirm this works propperly with the PSR with my latest fixes... </div></div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Sep 5, 2014 at 3:14 PM, Rodrigo Vivi <span dir="ltr"><<a href="mailto:rodrigo.vivi@gmail.com" target="_blank">rodrigo.vivi@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Hey Daniel, <div><br></div><div>funny story: Remember that with idle_frames=1 on BDW it was working but it was faililng on HSW?</div><div>So, with these 2 patches applied now BDW PSR fails like HSW!!!</div><div><br></div><div>Ville, any thoughts on this?</div></div><div class="gmail_extra"><div><div class="h5"><br><br><div class="gmail_quote">On Fri, Sep 5, 2014 at 1:57 PM, Rodrigo Vivi <span dir="ltr"><<a href="mailto:rodrigo.vivi@intel.com" target="_blank">rodrigo.vivi@intel.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">The sw cache clean on gen8 is a tempoorary workaround because we cannot<br>
set cache clean on blt ring with risk of hungs. So we are doing the cache clean on sw.<br>
However we are doing much more than needed. Not only when using blt ring.<br>
So, with this extra w/a we minimize the ammount of cache cleans and call it only<br>
on same cases that it was being called on gen7.<br>
<br>
fbc.need_sw_cache_clean works in the opposite information direction<br>
of ring->fbc_dirty telling software on frontbuffer tracking to perform<br>
the cache clean on sw side.<br>
<br>
Cc: Paulo Zanoni <<a href="mailto:paulo.r.zanoni@intel.com" target="_blank">paulo.r.zanoni@intel.com</a>><br>
Signed-off-by: Rodrigo Vivi <<a href="mailto:rodrigo.vivi@intel.com" target="_blank">rodrigo.vivi@intel.com</a>><br>
---<br>
drivers/gpu/drm/i915/i915_drv.h | 8 ++++++++<br>
drivers/gpu/drm/i915/intel_display.c | 4 +++-<br>
drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++++++--<br>
3 files changed, 18 insertions(+), 3 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h<br>
index 5706b8a..5acda40 100644<br>
--- a/drivers/gpu/drm/i915/i915_drv.h<br>
+++ b/drivers/gpu/drm/i915/i915_drv.h<br>
@@ -657,6 +657,14 @@ struct i915_fbc {<br>
<br>
bool false_color;<br>
<br>
+ /* On gen8 some rings cannont perform fbc clean operation so for now<br>
+ * we are doing this on SW with mmio.<br>
+ * This variable works in the opposite information direction<br>
+ * of ring->fbc_dirty telling software on frontbuffer tracking<br>
+ * to perform the cache clean on sw side.<br>
+ */<br>
+ bool need_sw_cache_clean;<br>
+<br>
struct intel_fbc_work {<br>
struct delayed_work work;<br>
struct drm_crtc *crtc;<br>
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c<br>
index 965eb3c..731d925 100644<br>
--- a/drivers/gpu/drm/i915/intel_display.c<br>
+++ b/drivers/gpu/drm/i915/intel_display.c<br>
@@ -9137,8 +9137,10 @@ void intel_frontbuffer_flush(struct drm_device *dev,<br>
* needs to be reworked into a proper frontbuffer tracking scheme like<br>
* psr employs.<br>
*/<br>
- if (IS_BROADWELL(dev))<br>
+ if (IS_BROADWELL(dev) && dev_priv->fbc.need_sw_cache_clean) {<br>
+ dev_priv->fbc.need_sw_cache_clean = false;<br>
gen8_fbc_sw_flush(dev, FBC_REND_CACHE_CLEAN);<br>
+ }<br>
}<br>
<br>
/**<br>
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c<br>
index 85fc2b1..02b43cd 100644<br>
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c<br>
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c<br>
@@ -2227,6 +2227,7 @@ static int gen6_ring_flush(struct intel_engine_cs *ring,<br>
u32 invalidate, u32 flush)<br>
{<br>
struct drm_device *dev = ring->dev;<br>
+ struct drm_i915_private *dev_priv = dev->dev_private;<br>
uint32_t cmd;<br>
int ret;<br>
<br>
@@ -2257,8 +2258,12 @@ static int gen6_ring_flush(struct intel_engine_cs *ring,<br>
}<br>
intel_ring_advance(ring);<br>
<br>
- if (IS_GEN7(dev) && !invalidate && flush)<br>
- return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);<br>
+ if (!invalidate && flush) {<br>
+ if (IS_GEN7(dev))<br>
+ return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);<br>
+ else if (IS_GEN8(dev))<br>
+ dev_priv->fbc.need_sw_cache_clean = true;<br>
+ }<br>
<br>
return 0;<br>
}<br>
<span><font color="#888888">--<br>
1.9.3<br>
<br>
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</font></span></blockquote></div><br><br clear="all"><div><br></div></div></div><span class="HOEnZb"><font color="#888888">-- <br><div>Rodrigo Vivi</div><div>Blog: <a href="http://blog.vivi.eng.br" target="_blank">http://blog.vivi.eng.br</a></div><div> </div>
</font></span></div>
</blockquote></div><br><br clear="all"><div><br></div>-- <br><div>Rodrigo Vivi</div><div>Blog: <a href="http://blog.vivi.eng.br" target="_blank">http://blog.vivi.eng.br</a></div><div> </div>
</div>