<div dir="ltr"> On Fri, Oct 31, 2014 at 5:27 AM, Rodrigo Vivi <<a href="mailto:rodrigo.vivi@intel.com">rodrigo.vivi@intel.com</a>> wrote: > > Global GTT doesn't have pat_sel[2:0] so it always point to pat_sel = 000; > So the only way to avoid screen corruptions is setting PAT 0 to Uncached. > > MOCS can still be used though. But if userspace is trusting PTE for > cache selection the safest thing to do is to let caches disabled. > > BSpec: "For GGTT, there is NO pat_sel[2:0] from the entry, > so RTL will always use the value corresponding to pat_sel = 000" > > v2: Cleaner patch as suggested by Chris. > > Reference: <a href="https://bugs.freedesktop.org/show_bug.cgi?id=85576">https://bugs.freedesktop.org/show_bug.cgi?id=85576</a> > Cc: Chris Wilson <<a href="mailto:chris@chris-wilson.co.uk">chris@chris-wilson.co.uk</a>> > Cc: James Ausmus <<a href="mailto:james.ausmus@intel.com">james.ausmus@intel.com</a>> > Signed-off-by: Rodrigo Vivi <<a href="mailto:rodrigo.vivi@intel.com">rodrigo.vivi@intel.com</a>> > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index cb7adab..ae568a2 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -1920,6 +1920,15 @@ static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) > GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | > GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); > > + if (!USES_PPGTT(dev_priv->dev)) > + /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, > + * so RTL will always use the value corresponding to > + * pat_sel = 000". > + * So let's disable cache for GGTT to avoid screen corruptions. > + * MOCS still can be used though. > + */ > + pat = GEN8_PPAT(0, GEN8_PPAT_UC); > + > /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b > * write would work. */ > I915_WRITE(GEN8_PRIVATE_PAT, pat); > -- > 1.9.3 > Tested-by: James Ausmus <<a href="mailto:james.ausmus@intel.com">james.ausmus@intel.com</a>> -- James Ausmus Sr. Software Engineer SSG-OTC ChromeOS Integration</div>