<div dir="ltr">I don't have the spec so I can just assume it was like previous platforms.<div><br></div><div>For me this 50MHz x 16.6MHz is still confusing (like clamp in 50 than convert to 16.6)... but nevermind... apparently we are not mixing stuff in the sense we compare values in different scales... </div><div><br></div><div>Reviewed-by: Rodrigo Vivi <<a href="mailto:rodrigo.vivi@intel.com">rodrigo.vivi@intel.com</a>></div><div><br></div><div><div><br></div></div></div><br><div class="gmail_quote"><div dir="ltr">On Mon, Jun 29, 2015 at 2:11 AM <<a href="mailto:akash.goel@intel.com">akash.goel@intel.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">From: Akash Goel <<a href="mailto:akash.goel@intel.com" target="_blank">akash.goel@intel.com</a>><br>
<br>
Read the efficient frequency (aka RPe) value through the the mailbox<br>
command (0x1A) from the pcode, as done on Haswell and Broadwell.<br>
The turbo minimum frequency softlimit is not revised as per the<br>
efficient frequency value.<br>
<br>
v2: Replaced the conditional expression operator with 'if' statement (Tom)<br>
v3: Corrected the derivation of efficient frequency & shifted the<br>
GEN9_FREQ_SCALER multiplications downwards (Ville)<br>
<br>
Issue: VIZ-5143<br>
Signed-off-by: Akash Goel <<a href="mailto:akash.goel@intel.com" target="_blank">akash.goel@intel.com</a>><br>
---<br>
drivers/gpu/drm/i915/intel_pm.c | 19 +++++++++++--------<br>
1 file changed, 11 insertions(+), 8 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c<br>
index 32ff034..8185a23 100644<br>
--- a/drivers/gpu/drm/i915/intel_pm.c<br>
+++ b/drivers/gpu/drm/i915/intel_pm.c<br>
@@ -4295,18 +4295,11 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)<br>
dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;<br>
dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;<br>
dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;<br>
- if (IS_SKYLAKE(dev)) {<br>
- /* Store the frequency values in 16.66 MHZ units, which is<br>
- the natural hardware unit for SKL */<br>
- dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;<br>
- dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;<br>
- dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;<br>
- }<br>
/* hw_max = RP0 until we check for overclocking */<br>
dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;<br>
<br>
dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;<br>
- if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {<br>
+ if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {<br>
ret = sandybridge_pcode_read(dev_priv,<br>
HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,<br>
&ddcc_status);<br>
@@ -4318,6 +4311,16 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)<br>
dev_priv->rps.max_freq);<br>
}<br>
<br>
+ if (IS_SKYLAKE(dev)) {<br>
+ /* Store the frequency values in 16.66 MHZ units, which is<br>
+ the natural hardware unit for SKL */<br>
+ dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;<br>
+ dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;<br>
+ dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;<br>
+ dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;<br>
+ dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;<br>
+ }<br>
+<br>
dev_priv->rps.idle_freq = dev_priv->rps.min_freq;<br>
<br>
/* Preserve min/max settings in case of re-init */<br>
--<br>
1.9.2<br>
<br>
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</blockquote></div>