<div dir="ltr">Sorry, but I don't get how this enables power_well_2 as well. I just see it enabling ddi A/E as the other. <div><br></div><div>Maybe Paulo or Imre are the best one to review this.</div></div><br><div class="gmail_quote"><div dir="ltr">On Thu, Aug 13, 2015 at 2:54 AM Xiong Zhang <<a href="mailto:xiong.y.zhang@intel.com">xiong.y.zhang@intel.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">From B spec, DDI_E port belong to PowerWell 2, but<br>
DDI_E share the powerwell_req/staus register bit with<br>
DDI_A which belong to DDI_A_E_POWER_WELL.<br>
<br>
In order to communicate with the connector on DDI-E, both<br>
DDI_A_E_POWER_WELL and POWER_WELL_2 must be enabled.<br>
<br>
Currently intel_dp_power_get(DDI_E) only enable<br>
DDI_A_E_POWER_WELL, this patch will not only enable<br>
DDI_a_E_POWER_WELL but also enable POWER_WELL_2.<br>
<br>
This patch also fix the DDI-E hotplug function.<br>
<br>
Signed-off-by: Xiong Zhang <<a href="mailto:xiong.y.zhang@intel.com" target="_blank">xiong.y.zhang@intel.com</a>><br>
---<br>
drivers/gpu/drm/i915/i915_debugfs.c | 2 ++<br>
drivers/gpu/drm/i915/i915_drv.h | 1 +<br>
drivers/gpu/drm/i915/intel_display.c | 3 ++-<br>
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 ++<br>
4 files changed, 7 insertions(+), 1 deletion(-)<br>
<br>
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c<br>
index 86734be..5523b6e 100644<br>
--- a/drivers/gpu/drm/i915/i915_debugfs.c<br>
+++ b/drivers/gpu/drm/i915/i915_debugfs.c<br>
@@ -2564,6 +2564,8 @@ static const char *power_domain_str(enum intel_display_power_domain domain)<br>
return "PORT_DDI_D_2_LANES";<br>
case POWER_DOMAIN_PORT_DDI_D_4_LANES:<br>
return "PORT_DDI_D_4_LANES";<br>
+ case POWER_DOMAIN_PORT_DDI_E_2_LANES:<br>
+ return "PORT_DDI_E_2_LANES";<br>
case POWER_DOMAIN_PORT_DSI:<br>
return "PORT_DSI";<br>
case POWER_DOMAIN_PORT_CRT:<br>
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h<br>
index b157865..ee71f90 100644<br>
--- a/drivers/gpu/drm/i915/i915_drv.h<br>
+++ b/drivers/gpu/drm/i915/i915_drv.h<br>
@@ -182,6 +182,7 @@ enum intel_display_power_domain {<br>
POWER_DOMAIN_PORT_DDI_C_4_LANES,<br>
POWER_DOMAIN_PORT_DDI_D_2_LANES,<br>
POWER_DOMAIN_PORT_DDI_D_4_LANES,<br>
+ POWER_DOMAIN_PORT_DDI_E_2_LANES,<br>
POWER_DOMAIN_PORT_DSI,<br>
POWER_DOMAIN_PORT_CRT,<br>
POWER_DOMAIN_PORT_OTHER,<br>
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c<br>
index 801187c..ccd3f0b 100644<br>
--- a/drivers/gpu/drm/i915/intel_display.c<br>
+++ b/drivers/gpu/drm/i915/intel_display.c<br>
@@ -5150,7 +5150,6 @@ static enum intel_display_power_domain port_to_power_domain(enum port port)<br>
{<br>
switch (port) {<br>
case PORT_A:<br>
- case PORT_E:<br>
return POWER_DOMAIN_PORT_DDI_A_4_LANES;<br>
case PORT_B:<br>
return POWER_DOMAIN_PORT_DDI_B_4_LANES;<br>
@@ -5158,6 +5157,8 @@ static enum intel_display_power_domain port_to_power_domain(enum port port)<br>
return POWER_DOMAIN_PORT_DDI_C_4_LANES;<br>
case PORT_D:<br>
return POWER_DOMAIN_PORT_DDI_D_4_LANES;<br>
+ case PORT_E:<br>
+ return POWER_DOMAIN_PORT_DDI_E_2_LANES;<br>
default:<br>
WARN_ON_ONCE(1);<br>
return POWER_DOMAIN_PORT_OTHER;<br>
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c<br>
index 821644d..af7fdb3 100644<br>
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c<br>
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c<br>
@@ -297,6 +297,7 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,<br>
BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \<br>
BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \<br>
BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \<br>
+ BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \<br>
BIT(POWER_DOMAIN_AUX_B) | \<br>
BIT(POWER_DOMAIN_AUX_C) | \<br>
BIT(POWER_DOMAIN_AUX_D) | \<br>
@@ -316,6 +317,7 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,<br>
#define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \<br>
BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \<br>
BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \<br>
+ BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \<br>
BIT(POWER_DOMAIN_INIT))<br>
#define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \<br>
BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \<br>
--<br>
2.1.4<br>
<br>
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</blockquote></div>