mesa: Branch 'i915tex-pageflip' - 3 commits

[Michel Daenzer]

 src/mesa/drivers/dri/i915tex/intel_buffers.c |   36 +++++++++++++++------------
 src/mesa/drivers/dri/i915tex/intel_fbo.c     |    6 +++-
 2 files changed, 25 insertions(+), 17 deletions(-)

New commits:
diff-tree 0609b6afa8117893d7b36468158ac6ec2f5642bc (from 3c578455e103664e6f93a7792999da7c06dd9a3f)
Author: Michel Dänzer <michel at tungstengraphics.com>
Date:   Wed Feb 28 17:46:07 2007 +0100

    i915tex: Sync pages differently when crossing pipe borders.
    
    Don't flip (up to twice) immediately but just arrange things such that the
    pages will be in sync on both pipes on the next flip.

diff --git a/src/mesa/drivers/dri/i915tex/intel_buffers.c b/src/mesa/drivers/dri/i915tex/intel_buffers.c
index 5eb2a8e..9f1b25e 100644
--- a/src/mesa/drivers/dri/i915tex/intel_buffers.c
+++ b/src/mesa/drivers/dri/i915tex/intel_buffers.c
@@ -253,19 +253,25 @@ intelWindowMoved(struct intel_context *i
 			 pf_active ? "" : "in");
 
       if (pf_active) {
-	 int i;
-
 	 /* Sync pages between pipes if we're flipping on both at the same time */
-	 for (i = 0; i < 2 && pf_pipes != intel_fb->pf_pipes &&
-		intel_fb->pf_pipes == 0x3 &&
-		(intel->sarea->pf_current_page & 0x3) !=
-		((intel->sarea->pf_current_page) >> 2 & 0x3); i++) {
-	    drm_i915_flip_t flip;
-
-	    flip.pipes = (intel_fb->pf_current_page ==
-			  (intel->sarea->pf_current_page & 0x3)) ? 0x2 : 0x1;
-
-	    drmCommandWrite(intel->driFd, DRM_I915_FLIP, &flip, sizeof(flip));
+	 if (pf_pipes == 0x3 &&	pf_pipes != intel_fb->pf_pipes &&
+	     (intel->sarea->pf_current_page & 0x3) !=
+	     (((intel->sarea->pf_current_page) >> 2) & 0x3)) {
+	    if (intel_fb->pf_current_page ==
+		(intel->sarea->pf_current_page & 0x3)) {
+	       /* XXX: This is ugly, but emitting two flips 'in a row' can cause
+		* lockups for unknown reasons.
+		*/
+               intel->sarea->pf_current_page =
+		  intel->sarea->pf_current_page & 0x3;
+	       intel->sarea->pf_current_page |=
+		  intel->sarea->pf_current_page << 2;
+	    } else {
+               intel->sarea->pf_current_page =
+		  intel->sarea->pf_current_page & (0x3 << 2);
+	       intel->sarea->pf_current_page |=
+		  intel->sarea->pf_current_page >> 2;
+	    }
 	 }
 
 	 intel_fb->pf_pipes = pf_pipes;
diff-tree 3c578455e103664e6f93a7792999da7c06dd9a3f (from edf676cc5af26d8f82625a94788d4f27c464ab38)
Author: Michel Dänzer <michel at tungstengraphics.com>
Date:   Wed Feb 28 17:42:54 2007 +0100

    i915tex: Check that intel_rb is valid before trying to add it to an fbo.

diff --git a/src/mesa/drivers/dri/i915tex/intel_fbo.c b/src/mesa/drivers/dri/i915tex/intel_fbo.c
index ad07845..8d43055 100644
--- a/src/mesa/drivers/dri/i915tex/intel_fbo.c
+++ b/src/mesa/drivers/dri/i915tex/intel_fbo.c
@@ -81,14 +81,16 @@ intel_flip_renderbuffers(struct intel_fr
    int current_page = intel_fb->pf_current_page;
    int next_page = (current_page + 1) % intel_fb->pf_num_pages;
 
-   if (intel_fb->Base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer !=
+   if (intel_fb->color_rb[current_page] &&
+       intel_fb->Base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer !=
        &intel_fb->color_rb[current_page]->Base) {
       _mesa_remove_renderbuffer(&intel_fb->Base, BUFFER_FRONT_LEFT);
       _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_FRONT_LEFT,
 			     &intel_fb->color_rb[current_page]->Base);
    }
 
-   if (intel_fb->Base.Attachment[BUFFER_BACK_LEFT].Renderbuffer !=
+   if (intel_fb->color_rb[next_page] &&
+       intel_fb->Base.Attachment[BUFFER_BACK_LEFT].Renderbuffer !=
        &intel_fb->color_rb[next_page]->Base) {
       _mesa_remove_renderbuffer(&intel_fb->Base, BUFFER_BACK_LEFT);
       _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_BACK_LEFT,
diff-tree edf676cc5af26d8f82625a94788d4f27c464ab38 (from 641c966e3de192eba17c693f00d6654742c72eb6)
Author: Michel Dänzer <michel at tungstengraphics.com>
Date:   Wed Feb 28 16:05:49 2007 +0100

    i915tex: Also update intel_rb->vbl_pending when scheduled swap is not a flip.

diff --git a/src/mesa/drivers/dri/i915tex/intel_buffers.c b/src/mesa/drivers/dri/i915tex/intel_buffers.c
index 8054d98..5eb2a8e 100644
--- a/src/mesa/drivers/dri/i915tex/intel_buffers.c
+++ b/src/mesa/drivers/dri/i915tex/intel_buffers.c
@@ -815,12 +815,12 @@ intelScheduleSwap(const __DRIdrawablePri
       swap.sequence -= target;
       *missed_target = swap.sequence > 0 && swap.sequence <= (1 << 23);
 
-      if (swap.seqtype & DRM_VBLANK_FLIP) {
+      intel_get_renderbuffer(&intel_fb->Base, BUFFER_BACK_LEFT)->vbl_pending =
 	 intel_get_renderbuffer(&intel_fb->Base,
 				BUFFER_FRONT_LEFT)->vbl_pending =
-	    intel_get_renderbuffer(&intel_fb->Base,
-				   BUFFER_BACK_LEFT)->vbl_pending = intel_fb->vbl_seq;
+	 intel_fb->vbl_seq;
 
+      if (swap.seqtype & DRM_VBLANK_FLIP) {
 	 intel_flip_renderbuffers(intel_fb);
 	 intel_draw_buffer(&intel->ctx, intel->ctx.DrawBuffer);
       }