mesa: Branch 'i915tex-pageflip' - 3 commits

[Michel Daenzer]

 src/mesa/drivers/dri/i915tex/intel_buffers.c |   33 +++++++++++++++++++++++++--
 src/mesa/drivers/dri/i915tex/intel_context.c |    2 -
 2 files changed, 32 insertions(+), 3 deletions(-)

New commits:
diff-tree 6e0878becfbf211e5bbd141cd3441dfbdb206cc8 (from bb0760ca4f1759eb3c237045f464da4ad60eef83)
Author: Michel Dänzer <michel at tungstengraphics.com>
Date:   Fri Mar 9 20:00:13 2007 +0100

    i915tex: Wait for pending scheduled flips before switching vsync pipe.
    
    This avoids hangs when the vblank sequence numbers are not in sync between
    pipes, in particular when they run at different refresh rates.

diff --git a/src/mesa/drivers/dri/i915tex/intel_buffers.c b/src/mesa/drivers/dri/i915tex/intel_buffers.c
index 174f3c6..1643957 100644
--- a/src/mesa/drivers/dri/i915tex/intel_buffers.c
+++ b/src/mesa/drivers/dri/i915tex/intel_buffers.c
@@ -300,8 +300,27 @@ intelWindowMoved(struct intel_context *i
       }
 
       if (flags != intel_fb->vblank_flags) {
+	 drmVBlank vbl;
+	 int i;
+
+	 vbl.request.type = DRM_VBLANK_ABSOLUTE;
+
+	 if ( intel_fb->vblank_flags & VBLANK_FLAG_SECONDARY ) {
+	    vbl.request.type |= DRM_VBLANK_SECONDARY;
+	 }
+
+	 for (i = 0; i < intel_fb->pf_num_pages; i++) {
+	    vbl.request.sequence = intel_fb->color_rb[i]->vbl_pending;
+	    drmWaitVBlank(intel->driFd, &vbl);
+	 }
+
 	 intel_fb->vblank_flags = flags;
 	 driGetCurrentVBlank(dPriv, intel_fb->vblank_flags, &intel_fb->vbl_seq);
+	 intel_fb->vbl_waited = intel_fb->vbl_seq;
+
+	 for (i = 0; i < intel_fb->pf_num_pages; i++) {
+	    intel_fb->color_rb[i]->vbl_pending = intel_fb->vbl_waited;
+	 }
       }
    } else {
       intel_fb->vblank_flags &= ~VBLANK_FLAG_SECONDARY;
diff-tree bb0760ca4f1759eb3c237045f464da4ad60eef83 (from 36b4e25da34691dffd6b147c8cf3d2598ec11ac7)
Author: Michel Dänzer <michel at tungstengraphics.com>
Date:   Fri Mar 9 19:56:55 2007 +0100

    i915tex: Set intel_fb->vbl_waited to current instead of what we aimed for.

diff --git a/src/mesa/drivers/dri/i915tex/intel_context.c b/src/mesa/drivers/dri/i915tex/intel_context.c
index b8515fe..5c2cdf0 100644
--- a/src/mesa/drivers/dri/i915tex/intel_context.c
+++ b/src/mesa/drivers/dri/i915tex/intel_context.c
@@ -730,7 +730,7 @@ void LOCK_HARDWARE( struct intel_context
 
 	vbl.request.sequence = intel_rb->vbl_pending;
 	drmWaitVBlank(intel->driFd, &vbl);
-	intel_fb->vbl_waited = intel_rb->vbl_pending;
+	intel_fb->vbl_waited = vbl.reply.sequence;
     }
 
     DRM_CAS(intel->driHwLock, intel->hHWContext,
diff-tree 36b4e25da34691dffd6b147c8cf3d2598ec11ac7 (from 81536789d2d2d92c687e9037cbb6f86b633ef839)
Author: Michel Dänzer <michel at tungstengraphics.com>
Date:   Fri Mar 9 17:52:29 2007 +0100

    i915tex: Sync pages between pipes immediately again.
    
    This should be safe now that we no longer use the MI_WAIT_FOR_EVENT instruction
    incorrectly and should also work correctly with applications that render to the
    front buffer.

diff --git a/src/mesa/drivers/dri/i915tex/intel_buffers.c b/src/mesa/drivers/dri/i915tex/intel_buffers.c
index 35236ed..174f3c6 100644
--- a/src/mesa/drivers/dri/i915tex/intel_buffers.c
+++ b/src/mesa/drivers/dri/i915tex/intel_buffers.c
@@ -257,6 +257,8 @@ intelWindowMoved(struct intel_context *i
 	 if (pf_pipes == 0x3 &&	pf_pipes != intel_fb->pf_pipes &&
 	     (intel->sarea->pf_current_page & 0x3) !=
 	     (((intel->sarea->pf_current_page) >> 2) & 0x3)) {
+	    drm_i915_flip_t flip;
+
 	    if (intel_fb->pf_current_page ==
 		(intel->sarea->pf_current_page & 0x3)) {
 	       /* XXX: This is ugly, but emitting two flips 'in a row' can cause
@@ -265,13 +267,21 @@ intelWindowMoved(struct intel_context *i
                intel->sarea->pf_current_page =
 		  intel->sarea->pf_current_page & 0x3;
 	       intel->sarea->pf_current_page |=
-		  intel->sarea->pf_current_page << 2;
+		  ((intel_fb->pf_current_page + intel_fb->pf_num_pages - 1) %
+		   intel_fb->pf_num_pages) << 2;
+
+	       flip.pipes = 0x2;
 	    } else {
                intel->sarea->pf_current_page =
 		  intel->sarea->pf_current_page & (0x3 << 2);
 	       intel->sarea->pf_current_page |=
-		  intel->sarea->pf_current_page >> 2;
+		  (intel_fb->pf_current_page + intel_fb->pf_num_pages - 1) %
+		  intel_fb->pf_num_pages;
+
+	       flip.pipes = 0x1;
 	    }
+
+	    drmCommandWrite(intel->driFd, DRM_I915_FLIP, &flip, sizeof(flip));
 	 }
 
 	 intel_fb->pf_pipes = pf_pipes;