mesa: Branch 'master' - 50 commits
Eric Anholt
anholt at kemper.freedesktop.org
Fri Mar 30 20:20:23 UTC 2007
src/mesa/drivers/dri/i965/intel_context.c | 3 +++
src/mesa/drivers/dri/i965/intel_context.h | 1 +
2 files changed, 4 insertions(+)
New commits:
diff-tree 57dadf71caab2fb85aad930e3e8df6cdc9db209a (from parents)
Merge: adb91c056f896955efcbf627bb1c2012aeb8a735 6f652c89d719f537425a8bd6f7e7909966a89a98
Author: Eric Anholt <eric at anholt.net>
Date: Fri Mar 30 13:18:27 2007 -0700
Merge branch 'origin'
diff-tree adb91c056f896955efcbf627bb1c2012aeb8a735 (from parents)
Merge: 7eba12edce871c3db835decbf1a0271acfd3eb68 ee9bc897f8ea361539c5f422fdecc2326271e673
Author: Eric Anholt <eric at anholt.net>
Date: Fri Mar 30 13:08:14 2007 -0700
Merge branch 'crestline-qa', adding support for the 965GM chipset.
diff-tree ee9bc897f8ea361539c5f422fdecc2326271e673 (from parents)
Merge: 1b354bb5e4c4524533a8f2c3293df73a403e011a 42aaa548a1020be5d40b3dce9448d8004b1ef947
Author: Nian Wu <nian.wu at intel.com>
Date: Mon Mar 26 17:00:29 2007 +0800
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree 1b354bb5e4c4524533a8f2c3293df73a403e011a (from parents)
Merge: 44fb5156bbda5e4fc1cd810fec5e50ac70ff39cf 74ceaf545feb530a61f2de1554c32d6ef0bd46f8
Author: Nian Wu <nian.wu at intel.com>
Date: Sun Mar 25 17:00:24 2007 +0800
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree 44fb5156bbda5e4fc1cd810fec5e50ac70ff39cf (from parents)
Merge: ad76128204d856527e033a83c1b5a35a2f52ba92 8e1c3bd0b4c599bae5b64cd51cec1d74266f30fb
Author: Nian Wu <nian.wu at intel.com>
Date: Sat Mar 24 17:00:29 2007 +0800
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree ad76128204d856527e033a83c1b5a35a2f52ba92 (from parents)
Merge: 2eb656ef4f4c7a365501e615a43ae72cfdc12cda 002762b13aa58ca569a564bb64672e343611c9ed
Author: Nian Wu <nian.wu at intel.com>
Date: Fri Mar 23 17:00:28 2007 +0800
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree 2eb656ef4f4c7a365501e615a43ae72cfdc12cda (from parents)
Merge: 8ba06464ac8de726390899e790e15b40df08001e 01b7f2ab2e7a9291bf54475e816e88804ee7cd53
Author: Nian Wu <nian.wu at intel.com>
Date: Thu Mar 22 17:00:33 2007 +0800
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree 8ba06464ac8de726390899e790e15b40df08001e (from parents)
Merge: 76444d042c841aa4e060db46c0668c17da97a1f6 4b5d6c0435acd84c13e0db3785758fed0bc48fe1
Author: Nian Wu <nian.wu at intel.com>
Date: Wed Mar 21 17:00:32 2007 +0800
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree 76444d042c841aa4e060db46c0668c17da97a1f6 (from parents)
Merge: e01ee3da577f177e77153f3a33d39e13f5e3f9cb ecb1a1c82f48dd78203230f6ea3dee49d7ade17d
Author: Nian Wu <nian.wu at intel.com>
Date: Tue Mar 20 13:10:46 2007 +0800
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree e01ee3da577f177e77153f3a33d39e13f5e3f9cb (from parents)
Merge: fd1b1fce3faaf40af201a5b06a84df62c855fb12 77544d7b7d7c6fd03c0df81dca07f1bb3a67c119
Author: Nian Wu <nian.wu at intel.com>
Date: Mon Mar 19 17:00:19 2007 +0800
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree fd1b1fce3faaf40af201a5b06a84df62c855fb12 (from parents)
Merge: 38889f5221821acf08365d3f332680707d4b9b5f cfe984dbd0c478906785dbf8a9430504173ae952
Author: Nian Wu <nian.wu at intel.com>
Date: Sun Mar 18 17:00:18 2007 +0800
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree 38889f5221821acf08365d3f332680707d4b9b5f (from parents)
Merge: a02870f4f61a66560b3eb75f98a7fe57ebcb6ed6 6a9b0cd0b43ba01b24871ec1fa155e192ddeaa56
Author: Nian Wu <nian.wu at intel.com>
Date: Sat Mar 17 17:00:25 2007 +0800
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree a02870f4f61a66560b3eb75f98a7fe57ebcb6ed6 (from parents)
Merge: d63eef4b86af02aea5b26f90de9cf3d46aee398c 95764262a7f2dfda761a0dbd87c3d9b12df0d534
Author: Nian Wu <nian.wu at intel.com>
Date: Fri Mar 16 17:00:24 2007 +0800
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree d63eef4b86af02aea5b26f90de9cf3d46aee398c (from parents)
Merge: 805b1cf4821aa807ce0f87d03dc464c0ee01a33a 32d196820f5669a03bfd1adde1352b857ffda3b6
Author: Nian Wu <nian.wu at intel.com>
Date: Thu Mar 15 17:00:22 2007 +0800
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree 805b1cf4821aa807ce0f87d03dc464c0ee01a33a (from parents)
Merge: 4110fac38958003935f64e278d3a7b880523efe2 a6cc9ab493a2efa9a0ea91cddba0e85c8c8c83f1
Author: Nian Wu <nian.wu at intel.com>
Date: Wed Mar 14 17:00:15 2007 +0800
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree 4110fac38958003935f64e278d3a7b880523efe2 (from parents)
Merge: 5a5b55943dfdb7fac77f7556058791302ee8639b eb4db4c4ec7efc366b00e1b1f1fe519ca1af79d6
Author: Nian Wu <nian.wu at intel.com>
Date: Tue Mar 13 17:00:18 2007 +0800
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree 5a5b55943dfdb7fac77f7556058791302ee8639b (from parents)
Merge: 1e055089a37bca8bc5e1cec37d5559fcdb0cf21f 61ec23cc63a040a2edf1bc466917e85362514c89
Author: Nian Wu <nian.wu at intel.com>
Date: Mon Mar 12 09:03:27 2007 +0800
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree 1e055089a37bca8bc5e1cec37d5559fcdb0cf21f (from parents)
Merge: 87c9ad6fd57a60c29dc83c8a538e70a93d125e25 2282d815360c2087dd080c794084bea65e6da358
Author: Nian Wu <nian.wu at intel.com>
Date: Wed Mar 7 16:01:36 2007 -0500
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree 87c9ad6fd57a60c29dc83c8a538e70a93d125e25 (from parents)
Merge: c05b6f800a1d4726ea92a20aab99dde5d00b5e17 1c70cde8881f794782780cbd695da0882f78c769
Author: Nian Wu <nian.wu at intel.com>
Date: Tue Mar 6 16:01:23 2007 -0500
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree c05b6f800a1d4726ea92a20aab99dde5d00b5e17 (from parents)
Merge: 540e1c70ccb756200dbec3441b8238fac8e1cebe a783713432a1aed168688ace7d03bc11abf9b406
Author: Nian Wu <nian.wu at intel.com>
Date: Tue Mar 6 07:43:03 2007 -0500
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree 540e1c70ccb756200dbec3441b8238fac8e1cebe (from parents)
Merge: 180c0d70c43abe694e8b601159e02baf9af7b042 7ecdfb2f08c8722ecad9269ef753420a49be3dde
Author: Nian Wu <nian.wu at intel.com>
Date: Mon Mar 5 09:01:31 2007 -0500
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree 180c0d70c43abe694e8b601159e02baf9af7b042 (from parents)
Merge: 6a47e350656b1090e399144ff6a0cdabe94842e7 95577064040ceeaaf7b0a460f91eac951cf8af18
Author: Nian Wu <nian.wu at intel.com>
Date: Fri Mar 2 09:01:27 2007 -0500
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree 6a47e350656b1090e399144ff6a0cdabe94842e7 (from parents)
Merge: 381b4b0c91d476811420d8806eb8c058d0075927 38a88db1fc69b774ded3b7a44126e0b0f61e886b
Author: Nian Wu <nian.wu at intel.com>
Date: Thu Mar 1 09:01:58 2007 -0500
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree 381b4b0c91d476811420d8806eb8c058d0075927 (from parents)
Merge: 675f7f627bec92315bf168a9c872ffc05f88c69c e21096b07c5854d01114b58f87d08709e370f8b7
Author: Nian Wu <nian at tinderbox.sh.intel.com>
Date: Tue Feb 27 14:42:16 2007 -0500
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree 675f7f627bec92315bf168a9c872ffc05f88c69c (from parents)
Merge: 51bfb8fc8c78bb066d24e6ecbc20f00af7210386 c080123998f28d9317331aec7ddfcd1074b29daf
Author: Nian Wu <nian at graphics.(none)>
Date: Sun Feb 25 09:40:28 2007 -0800
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree 51bfb8fc8c78bb066d24e6ecbc20f00af7210386 (from 6b6760d6bc23b98ee1de27ba78189e56e248ce9b)
Author: Wang Zhenyu <zhenyu.z.wang at intel.com>
Date: Fri Feb 2 10:04:48 2007 +0800
Add Intel 965GM chipset info
diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 388600d..fea6e44 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -119,6 +119,9 @@ static const GLubyte *intelGetString( GL
case PCI_CHIP_I946_GZ:
chipset = "Intel(R) 946GZ"; break;
break;
+ case PCI_CHIP_I965_GM:
+ chipset = "Intel(R) 965GM"; break;
+ break;
default:
chipset = "Unknown Intel Chipset"; break;
}
diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index d51536c..74a795c 100644
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -384,6 +384,7 @@ extern int INTEL_DEBUG;
#define PCI_CHIP_I965_Q 0x2992
#define PCI_CHIP_I965_G_1 0x2982
#define PCI_CHIP_I946_GZ 0x2972
+#define PCI_CHIP_I965_GM 0x2A02
/* ================================================================
diff-tree 6b6760d6bc23b98ee1de27ba78189e56e248ce9b (from c171166987167db5e8ff67a09327283c0ef1b222)
Author: Wang Zhenyu <zhenyu.z.wang at intel.com>
Date: Fri Feb 2 10:01:42 2007 +0800
Revert origin crestline pci id patch
diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index f730ea0..388600d 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -119,9 +119,6 @@ static const GLubyte *intelGetString( GL
case PCI_CHIP_I946_GZ:
chipset = "Intel(R) 946GZ"; break;
break;
- case PCI_CHIP_CRESTLINE:
- chipset = "Intel(R) Crestline"; break;
- break;
default:
chipset = "Unknown Intel Chipset"; break;
}
diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index d971b7e..d51536c 100644
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -384,7 +384,6 @@ extern int INTEL_DEBUG;
#define PCI_CHIP_I965_Q 0x2992
#define PCI_CHIP_I965_G_1 0x2982
#define PCI_CHIP_I946_GZ 0x2972
-#define PCI_CHIP_CRESTLINE 0x2A02
/* ================================================================
diff-tree c171166987167db5e8ff67a09327283c0ef1b222 (from a27d3e43fe98837a851a6c0f6f0605f83a002187)
Author: Zou Nan hai <nanhai.zou at intel.com>
Date: Thu Jan 18 14:41:38 2007 +0800
1. Fix bug #155
2. I notice multiple ARB_occlusion_query should be able to overlap according to spec.
3. Declaring extern variables in a .c file is evil, fix it.
diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 0daa0ec..f730ea0 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -187,9 +187,17 @@ const struct dri_extension card_extensio
{ NULL, NULL }
};
-static const struct dri_extension arb_oc_extension =
+const struct dri_extension arb_oc_extension =
{ "GL_ARB_occlusion_query", GL_ARB_occlusion_query_functions};
+void intelInitExtensions(GLcontext *ctx, GLboolean enable_imaging)
+{
+ struct intel_context *intel = ctx?intel_context(ctx):NULL;
+ driInitExtensions(ctx, card_extensions, enable_imaging);
+ if (!ctx || intel->intelScreen->drmMinor >= 8)
+ driInitSingleExtension (ctx, &arb_oc_extension);
+}
+
static const struct dri_debug_control debug_control[] =
{
{ "fall", DEBUG_FALLBACKS },
@@ -251,28 +259,29 @@ static void
intelBeginQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q)
{
struct intel_context *intel = intel_context( ctx );
- GLuint64EXT tmp = 0;
drmI830MMIO io = {
.read_write = MMIO_WRITE,
.reg = MMIO_REGS_PS_DEPTH_COUNT,
- .data = &tmp
+ .data = &q->Result
};
intel->stats_wm = GL_TRUE;
intelFinish(&intel->ctx);
- drmCommandWrite(intel->driFd, DRM_I830_MMIO, &io, sizeof(io));
+ drmCommandRead(intel->driFd, DRM_I830_MMIO, &io, sizeof(io));
}
static void
intelEndQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q)
{
struct intel_context *intel = intel_context( ctx );
+ GLuint64EXT tmp;
drmI830MMIO io = {
.read_write = MMIO_READ,
.reg = MMIO_REGS_PS_DEPTH_COUNT,
- .data = &q->Result
+ .data = &tmp
};
intelFinish(&intel->ctx);
drmCommandRead(intel->driFd, DRM_I830_MMIO, &io, sizeof(io));
+ q->Result = tmp - q->Result;
q->Ready = GL_TRUE;
intel->stats_wm = GL_FALSE;
}
@@ -412,12 +421,7 @@ GLboolean intelInitContext( struct intel
_mesa_printf("IRQs not active. Exiting\n");
exit(1);
}
-
- driInitExtensions( ctx, card_extensions,
- GL_TRUE );
-
- if (intel->intelScreen->drmMinor >= 8)
- driInitSingleExtension (ctx, &arb_oc_extension);
+ intelInitExtensions(ctx, GL_TRUE);
INTEL_DEBUG = driParseDebugString( getenv( "INTEL_DEBUG" ),
debug_control );
@@ -696,3 +700,4 @@ void UNLOCK_HARDWARE( struct intel_conte
_glthread_UNLOCK_MUTEX(lockMutex);
}
+
diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index 39eb775..d971b7e 100644
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -501,6 +501,7 @@ void intelBitmap(GLcontext * ctx,
const struct gl_pixelstore_attrib *unpack,
const GLubyte * pixels);
+void intelInitExtensions(GLcontext *ctx, GLboolean enable_imaging);
#define _NEW_WINDOW_POS 0x40000000
@@ -523,6 +524,5 @@ static inline struct intel_texture_image
return (struct intel_texture_image *)img;
}
-
#endif
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 8269deb..08f0bb3 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -38,6 +38,7 @@
#include "intel_screen.h"
+#include "intel_context.h"
#include "intel_tex.h"
#include "intel_span.h"
#include "intel_ioctl.h"
@@ -61,8 +62,6 @@ const GLuint __driNConfigOptions = 4;
static PFNGLXCREATECONTEXTMODES create_context_modes = NULL;
#endif /*USE_NEW_INTERFACE*/
-extern const struct dri_extension card_extensions[];
-
/**
* Map all the memory regions described by the screen.
* \return GL_TRUE if success, GL_FALSE if error.
@@ -687,7 +686,6 @@ void * __driCreateNewScreen_20050727( __
(dri_priv->cpp == 2) ? 16 : 24,
(dri_priv->cpp == 2) ? 0 : 8,
GL_TRUE );
-
/* Calling driInitExtensions here, with a NULL context pointer, does not actually
* enable the extensions. It just makes sure that all the dispatch offsets for all
* the extensions that *might* be enables are known. This is needed because the
@@ -696,7 +694,7 @@ void * __driCreateNewScreen_20050727( __
*
* Hello chicken. Hello egg. How are you two today?
*/
- driInitExtensions( NULL, card_extensions, GL_FALSE );
+ intelInitExtensions(NULL, GL_FALSE);
}
return (void *) psp;
diff-tree a27d3e43fe98837a851a6c0f6f0605f83a002187 (from parents)
Merge: 6a632de96dca87a28fe03afb3a9bac3b4a3519d7 d9dd9013a8530bcafcdb2c5fed2b01a22bfca69b
Author: Keith Packard <keithp at neko.keithp.com>
Date: Sun Jan 7 23:03:01 2007 -0800
Merge branch 'master' into crestline
diff-tree 6a632de96dca87a28fe03afb3a9bac3b4a3519d7 (from parents)
Merge: 92de58f00162a6b3c40bf12635f3ee4f0480e09a 026939b00897665f97669bafb1d486a71f90f935
Author: Keith Packard <keithp at neko.keithp.com>
Date: Sun Jan 7 20:57:56 2007 -0800
Merge branch 'origin' into crestline
diff-tree 92de58f00162a6b3c40bf12635f3ee4f0480e09a (from parents)
Merge: caf8010652f77e7687c0a3b7c267ba49d0a24d74 62db3cc34982d2fec9165633813ef6e656f7d497
Author: Keith Packard <keithp at neko.keithp.com>
Date: Sat Jan 6 17:14:14 2007 -0800
Merge branch 'master' into crestline
diff-tree caf8010652f77e7687c0a3b7c267ba49d0a24d74 (from parents)
Merge: f34cad0f972ca838cb223429acab54d26c2f6a57 8c1cc5fd8084e7a927b15c88709a615fa16b06a3
Author: Wang Zhenyu <zhenyu.z.wang at intel.com>
Date: Mon Dec 4 15:48:04 2006 +0800
Merge branch 'master' into crestline
Conflicts:
src/mesa/drivers/dri/i965/brw_tex_layout.c
Michel Dänzer replaced the copy of the 945 mipmap layout code with that from
the 945 driver directly.
diff-tree f34cad0f972ca838cb223429acab54d26c2f6a57 (from parents)
Merge: ead0f46d5f9213f03f6c4b956aa96eda8fd0f1df adccb084df57ea5aef1b2ff9c21038ce1b89f7e3
Author: Nian Wu <nian at graphics.(none)>
Date: Tue Dec 26 16:46:51 2006 -0800
Merge branch 'crestline' into crestline-qa
diff-tree adccb084df57ea5aef1b2ff9c21038ce1b89f7e3 (from 77b862a84910713760665ca5af5e27fba48466dc)
Author: Haihao Xiang <haihao.xiang at intel.com>
Date: Tue Dec 26 16:45:02 2006 -0800
Support linear format in i965.
Fix bug #117 #118
diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 6bcc984..1546b33 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -440,7 +440,7 @@ GLboolean intelInitContext( struct intel
intelScreen->cpp,
intelScreen->front.pitch / intelScreen->cpp,
intelScreen->height,
- GL_FALSE);
+ intelScreen->front.tiled != 0); /* 0: LINEAR */
intel->back_region =
@@ -451,7 +451,7 @@ GLboolean intelInitContext( struct intel
intelScreen->cpp,
intelScreen->back.pitch / intelScreen->cpp,
intelScreen->height,
- (INTEL_DEBUG & DEBUG_TILE) ? 0 : 1);
+ intelScreen->back.tiled != 0);
/* Still assuming front.cpp == depth.cpp
*
@@ -467,7 +467,7 @@ GLboolean intelInitContext( struct intel
intelScreen->cpp,
intelScreen->depth.pitch / intelScreen->cpp,
intelScreen->height,
- (INTEL_DEBUG & DEBUG_TILE) ? 0 : 1);
+ intelScreen->depth.tiled != 0);
intel_bufferobj_init( intel );
intel->batch = intel_batchbuffer_alloc( intel );
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 56e6a79..8269deb 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -230,16 +230,19 @@ intelUpdateScreenFromSAREA(intelScreenPr
intelScreen->front.pitch = sarea->pitch * intelScreen->cpp;
intelScreen->front.handle = sarea->front_handle;
intelScreen->front.size = sarea->front_size;
+ intelScreen->front.tiled = sarea->front_tiled;
intelScreen->back.offset = sarea->back_offset;
intelScreen->back.pitch = sarea->pitch * intelScreen->cpp;
intelScreen->back.handle = sarea->back_handle;
intelScreen->back.size = sarea->back_size;
-
+ intelScreen->back.tiled = sarea->back_tiled;
+
intelScreen->depth.offset = sarea->depth_offset;
intelScreen->depth.pitch = sarea->pitch * intelScreen->cpp;
intelScreen->depth.handle = sarea->depth_handle;
intelScreen->depth.size = sarea->depth_size;
+ intelScreen->depth.tiled = sarea->depth_tiled;
intelScreen->tex.offset = sarea->tex_offset;
intelScreen->logTextureGranularity = sarea->log_tex_granularity;
@@ -249,6 +252,7 @@ intelUpdateScreenFromSAREA(intelScreenPr
intelScreen->rotated.offset = sarea->rotated_offset;
intelScreen->rotated.pitch = sarea->rotated_pitch * intelScreen->cpp;
intelScreen->rotated.size = sarea->rotated_size;
+ intelScreen->rotated.tiled = sarea->rotated_tiled;
intelScreen->current_rotation = sarea->rotation;
#if 0
matrix23Rotate(&intelScreen->rotMatrix,
diff --git a/src/mesa/drivers/dri/i965/intel_screen.h b/src/mesa/drivers/dri/i965/intel_screen.h
index 094158a..bf9a716 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.h
+++ b/src/mesa/drivers/dri/i965/intel_screen.h
@@ -42,6 +42,7 @@ typedef struct {
char *map; /* memory map */
int offset; /* from start of video mem, in bytes */
int pitch; /* row stride, in pixels */
+ unsigned int tiled;
} intelRegion;
typedef struct
diff-tree ead0f46d5f9213f03f6c4b956aa96eda8fd0f1df (from parents)
Merge: c34d026eb001a9178119ed7cdf70a7311cdc263f 77b862a84910713760665ca5af5e27fba48466dc
Author: Nian Wu <nian at graphics.(none)>
Date: Sun Dec 17 10:49:43 2006 -0800
Merge branch 'crestline' into crestline-qa
diff-tree 77b862a84910713760665ca5af5e27fba48466dc (from parents)
Merge: ed7fbad2066f846bf9466b13b184a50d6f87f972 2956a0c8a8395e4d9ae00888aeb88ea5c38b89ad
Author: Nian Wu <nian.wu at intel.com>
Date: Wed Dec 13 13:49:00 2006 -0800
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
diff-tree ed7fbad2066f846bf9466b13b184a50d6f87f972 (from 4720cd00507f2c13becf318709f7c1fe24ba5146)
Author: Zou Nan hai <nanhai.zou at intel.com>
Date: Wed Dec 13 15:22:45 2006 +0800
Fix bug #93, i965 driver not thread safe.
I am not confident of it is 100% thread safe now.
bufmgr_fake.c need a total rewrite later
(cherry picked from 606632ca27558ee1335be2f4a5906f2baa240a6a commit)
diff --git a/src/mesa/drivers/dri/i965/bufmgr.h b/src/mesa/drivers/dri/i965/bufmgr.h
index 6932522..e748c0d 100644
--- a/src/mesa/drivers/dri/i965/bufmgr.h
+++ b/src/mesa/drivers/dri/i965/bufmgr.h
@@ -199,9 +199,11 @@ void *bmFindVirtual( struct intel_contex
* For now they can stay, but will likely change/move before final:
*/
unsigned bmSetFence( struct intel_context * );
+unsigned bmSetFenceLock( struct intel_context * );
unsigned bmLockAndFence( struct intel_context *intel );
int bmTestFence( struct intel_context *, unsigned fence );
void bmFinishFence( struct intel_context *, unsigned fence );
+void bmFinishFenceLock( struct intel_context *, unsigned fence );
void bm_fake_NotifyContendedLockTake( struct intel_context * );
diff --git a/src/mesa/drivers/dri/i965/bufmgr_fake.c b/src/mesa/drivers/dri/i965/bufmgr_fake.c
index ed88ab3..205dc72 100644
--- a/src/mesa/drivers/dri/i965/bufmgr_fake.c
+++ b/src/mesa/drivers/dri/i965/bufmgr_fake.c
@@ -338,7 +338,6 @@ static int evict_mru( struct intel_conte
}
-
static int check_fenced( struct intel_context *intel )
{
struct bufmgr *bm = intel->bm;
@@ -1328,11 +1327,19 @@ unsigned bmSetFence( struct intel_contex
return intel->bm->last_fence;
}
+unsigned bmSetFenceLock( struct intel_context *intel )
+{
+ LOCK(intel->bm);
+ bmSetFence(intel);
+ UNLOCK(intel->bm);
+}
unsigned bmLockAndFence( struct intel_context *intel )
{
if (intel->bm->need_fence) {
LOCK_HARDWARE(intel);
+ LOCK(intel->bm);
bmSetFence(intel);
+ UNLOCK(intel->bm);
UNLOCK_HARDWARE(intel);
}
@@ -1350,7 +1357,12 @@ void bmFinishFence( struct intel_context
check_fenced(intel);
}
-
+void bmFinishFenceLock( struct intel_context *intel, unsigned fence )
+{
+ LOCK(intel->bm);
+ bmFinishFence(intel, fence);
+ UNLOCK(intel->bm);
+}
/* Specifically ignore texture memory sharing.
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index c8c5bf9..173d1d5 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -66,7 +66,7 @@ void intelCopyBuffer( const __DRIdrawabl
intelFlush( &intel->ctx );
- bmFinishFence(intel, intel->last_swap_fence);
+ bmFinishFenceLock(intel, intel->last_swap_fence);
/* The LOCK_HARDWARE is required for the cliprects. Buffer offsets
* should work regardless.
@@ -155,7 +155,7 @@ void intelCopyBuffer( const __DRIdrawabl
intel_batchbuffer_flush( intel->batch );
intel->second_last_swap_fence = intel->last_swap_fence;
- intel->last_swap_fence = bmSetFence( intel );
+ intel->last_swap_fence = bmSetFenceLock( intel );
UNLOCK_HARDWARE( intel );
if (!rect)
diff-tree 4720cd00507f2c13becf318709f7c1fe24ba5146 (from c9795c6ca253b25b2b15967b064f32d9b822a1c8)
Author: Zou Nan hai <nanhai.zou at intel.com>
Date: Tue Dec 12 14:56:59 2006 +0800
fix bug #99.
prim_count overflow when there is more than 1 cliprect
(cherry picked from 84b958d66fe7d3fe03ed12b493e3f3197f656531 commit)
diff --git a/src/mesa/drivers/dri/i965/brw_exec_api.c b/src/mesa/drivers/dri/i965/brw_exec_api.c
index 470fa6f..8b243c6 100644
--- a/src/mesa/drivers/dri/i965/brw_exec_api.c
+++ b/src/mesa/drivers/dri/i965/brw_exec_api.c
@@ -42,6 +42,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "dispatch.h"
#include "brw_exec.h"
+#include "intel_context.h"
+
static void reset_attrfv( struct brw_exec_context *exec );
@@ -522,6 +524,14 @@ static void GLAPIENTRY brw_exec_Begin( G
}
+static GLuint brw_max_prim( GLcontext *ctx )
+{
+ struct intel_context *intel = intel_context( ctx );
+ if (intel->numClipRects <= 1)
+ return BRW_MAX_PRIM;
+ return BRW_MAX_PRIM/intel->numClipRects;
+}
+
static void GLAPIENTRY brw_exec_End( void )
{
GET_CURRENT_CONTEXT( ctx );
@@ -536,7 +546,7 @@ static void GLAPIENTRY brw_exec_End( voi
ctx->Driver.CurrentExecPrimitive = GL_POLYGON+1;
- if (exec->vtx.prim_count == BRW_MAX_PRIM)
+ if (exec->vtx.prim_count >= brw_max_prim(ctx))
brw_exec_vtx_flush( exec );
}
else
diff-tree c9795c6ca253b25b2b15967b064f32d9b822a1c8 (from bce82efe1fc57f88dc050f5c13508b2e442b7a0d)
Author: Michel Dänzer <michel at tungstengraphics.com>
Date: Mon Dec 11 17:45:06 2006 +0100
minstall: Pass correct destination file path to $RM regardless of source path.
(cherry picked from 26626c0052cd5442f609659aa9ed25ac78e65b55 commit)
diff --git a/bin/minstall b/bin/minstall
index 210c275..819b2bc 100755
--- a/bin/minstall
+++ b/bin/minstall
@@ -65,7 +65,7 @@ if [ $# -ge 2 ] ; then
elif [ -f "$FILE" ] ; then
#echo "$FILE" is a regular file
- $RM "$DEST/$FILE"
+ $RM "$DEST/`basename $FILE`"
cp "$FILE" "$DEST"
if [ $MODE ] ; then
FILE=`basename "$FILE"`
diff-tree bce82efe1fc57f88dc050f5c13508b2e442b7a0d (from aeda4c589ada4e6304577e55d55b5c50bc274793)
Author: Michel Dänzer <michel at tungstengraphics.com>
Date: Mon Dec 11 17:36:35 2006 +0100
minstall: Always remove destination file before (re-)creating it.
This avoids issues with overwriting files that are being used.
(cherry picked from d71a5647a3ed4aadd46edfa8a031ffc87d88c5f7 commit)
diff --git a/bin/minstall b/bin/minstall
index 9795263..210c275 100755
--- a/bin/minstall
+++ b/bin/minstall
@@ -65,6 +65,7 @@ if [ $# -ge 2 ] ; then
elif [ -f "$FILE" ] ; then
#echo "$FILE" is a regular file
+ $RM "$DEST/$FILE"
cp "$FILE" "$DEST"
if [ $MODE ] ; then
FILE=`basename "$FILE"`
diff-tree aeda4c589ada4e6304577e55d55b5c50bc274793 (from 696fe3f52e0e7893740b430835f8c95611de3dd3)
Author: Zou Nan hai <nanhai.zou at intel.com>
Date: Wed Dec 13 13:25:12 2006 -0800
ARB_occlusion_query support
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index 4707a70..e41042d 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -168,7 +168,7 @@ static void upload_wm_unit(struct brw_co
wm.wm5.line_stipple = 1;
}
- if (INTEL_DEBUG & DEBUG_STATS)
+ if (INTEL_DEBUG & DEBUG_STATS || intel->stats_wm)
wm.wm4.stats_enable = 1;
brw->wm.state_gs_offset = brw_cache_data( &brw->cache[BRW_WM_UNIT], &wm );
diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 5fc3d71..6bcc984 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -70,6 +70,7 @@ int INTEL_DEBUG = (0);
#define need_GL_ARB_vertex_buffer_object
#define need_GL_ARB_vertex_program
#define need_GL_ARB_window_pos
+#define need_GL_ARB_occlusion_query
#define need_GL_EXT_blend_color
#define need_GL_EXT_blend_equation_separate
#define need_GL_EXT_blend_func_separate
@@ -160,6 +161,7 @@ const struct dri_extension card_extensio
{ "GL_ARB_vertex_buffer_object", GL_ARB_vertex_buffer_object_functions },
{ "GL_ARB_vertex_program", GL_ARB_vertex_program_functions },
{ "GL_ARB_window_pos", GL_ARB_window_pos_functions },
+ { "GL_ARB_occlusion_query", GL_ARB_occlusion_query_functions},
{ "GL_EXT_blend_color", GL_EXT_blend_color_functions },
{ "GL_EXT_blend_equation_separate", GL_EXT_blend_equation_separate_functions },
{ "GL_EXT_blend_func_separate", GL_EXT_blend_func_separate_functions },
@@ -244,6 +246,36 @@ void intelFinish( GLcontext *ctx )
bmFinishFence(intel, bmLockAndFence(intel));
}
+static void
+intelBeginQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q)
+{
+ struct intel_context *intel = intel_context( ctx );
+ GLuint64EXT tmp = 0;
+ drmI830MMIO io = {
+ .read_write = MMIO_WRITE,
+ .reg = MMIO_REGS_PS_DEPTH_COUNT,
+ .data = &tmp
+ };
+ intel->stats_wm = GL_TRUE;
+ intelFinish(&intel->ctx);
+ drmCommandWrite(intel->driFd, DRM_I830_MMIO, &io, sizeof(io));
+}
+
+static void
+intelEndQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q)
+{
+ struct intel_context *intel = intel_context( ctx );
+ drmI830MMIO io = {
+ .read_write = MMIO_READ,
+ .reg = MMIO_REGS_PS_DEPTH_COUNT,
+ .data = &q->Result
+ };
+ intelFinish(&intel->ctx);
+ drmCommandRead(intel->driFd, DRM_I830_MMIO, &io, sizeof(io));
+ q->Ready = GL_TRUE;
+ intel->stats_wm = GL_FALSE;
+}
+
void intelInitDriverFunctions( struct dd_function_table *functions )
{
@@ -253,6 +285,8 @@ void intelInitDriverFunctions( struct dd
functions->Finish = intelFinish;
functions->GetString = intelGetString;
functions->UpdateState = intelInvalidateState;
+ functions->BeginQuery = intelBeginQuery;
+ functions->EndQuery = intelEndQuery;
/* CopyPixels can be accelerated even with the current memory
* manager:
diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index 85e574c..39eb775 100644
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -177,6 +177,7 @@ struct intel_context
GLuint second_last_swap_fence;
GLboolean aub_wrap;
+ GLboolean stats_wm;
struct intel_batchbuffer *batch;
diff --git a/src/mesa/drivers/dri/i965/server/i830_common.h b/src/mesa/drivers/dri/i965/server/i830_common.h
index e3bbdc7..f320378 100644
--- a/src/mesa/drivers/dri/i965/server/i830_common.h
+++ b/src/mesa/drivers/dri/i965/server/i830_common.h
@@ -52,6 +52,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#define DRM_I830_INIT_HEAP 0x0a
#define DRM_I830_CMDBUFFER 0x0b
#define DRM_I830_DESTROY_HEAP 0x0c
+#define DRM_I830_MMIO 0x10
typedef struct {
enum {
@@ -199,5 +200,23 @@ typedef struct {
int region;
} drmI830MemDestroyHeap;
+#define MMIO_READ 0
+#define MMIO_WRITE 1
+
+#define MMIO_REGS_IA_PRIMATIVES_COUNT 0
+#define MMIO_REGS_IA_VERTICES_COUNT 1
+#define MMIO_REGS_VS_INVOCATION_COUNT 2
+#define MMIO_REGS_GS_PRIMITIVES_COUNT 3
+#define MMIO_REGS_GS_INVOCATION_COUNT 4
+#define MMIO_REGS_CL_PRIMITIVES_COUNT 5
+#define MMIO_REGS_CL_INVOCATION_COUNT 6
+#define MMIO_REGS_PS_INVOCATION_COUNT 7
+#define MMIO_REGS_PS_DEPTH_COUNT 8
+
+typedef struct {
+ unsigned int read_write:1;
+ unsigned int reg:31;
+ void __user *data;
+} drmI830MMIO;
#endif /* _I830_DRM_H_ */
diff-tree 696fe3f52e0e7893740b430835f8c95611de3dd3 (from 9a94dae4c292bfc2aa94a3f86865550e2217b870)
Author: Zou Nan hai <nanhai.zou at intel.com>
Date: Wed Dec 13 13:24:35 2006 -0800
if (tex width < 4), mipmap calculation will be out of range
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 1353325..bf7047f 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -138,7 +138,7 @@ GLboolean brw_miptree_layout( struct int
/* Layout_below: step right after second mipmap.
*/
- if (level == mt->first_level + 1) {
+ if (level == mt->first_level + 1 && mt->pitch > 4) {
x += mt->pitch / 2;
x = (x + 3) & ~ 3;
}
diff-tree c34d026eb001a9178119ed7cdf70a7311cdc263f (from de90bbd0b7c7b8569209770e9294fd967e10dac5)
Author: Zou Nan hai <nanhai.zou at intel.com>
Date: Wed Dec 13 15:27:17 2006 +0800
Fix bug #93
diff --git a/src/mesa/drivers/dri/i965/bufmgr.h b/src/mesa/drivers/dri/i965/bufmgr.h
index 6932522..e748c0d 100644
--- a/src/mesa/drivers/dri/i965/bufmgr.h
+++ b/src/mesa/drivers/dri/i965/bufmgr.h
@@ -199,9 +199,11 @@ void *bmFindVirtual( struct intel_contex
* For now they can stay, but will likely change/move before final:
*/
unsigned bmSetFence( struct intel_context * );
+unsigned bmSetFenceLock( struct intel_context * );
unsigned bmLockAndFence( struct intel_context *intel );
int bmTestFence( struct intel_context *, unsigned fence );
void bmFinishFence( struct intel_context *, unsigned fence );
+void bmFinishFenceLock( struct intel_context *, unsigned fence );
void bm_fake_NotifyContendedLockTake( struct intel_context * );
diff --git a/src/mesa/drivers/dri/i965/bufmgr_fake.c b/src/mesa/drivers/dri/i965/bufmgr_fake.c
index ed88ab3..205dc72 100644
--- a/src/mesa/drivers/dri/i965/bufmgr_fake.c
+++ b/src/mesa/drivers/dri/i965/bufmgr_fake.c
@@ -338,7 +338,6 @@ static int evict_mru( struct intel_conte
}
-
static int check_fenced( struct intel_context *intel )
{
struct bufmgr *bm = intel->bm;
@@ -1328,11 +1327,19 @@ unsigned bmSetFence( struct intel_contex
return intel->bm->last_fence;
}
+unsigned bmSetFenceLock( struct intel_context *intel )
+{
+ LOCK(intel->bm);
+ bmSetFence(intel);
+ UNLOCK(intel->bm);
+}
unsigned bmLockAndFence( struct intel_context *intel )
{
if (intel->bm->need_fence) {
LOCK_HARDWARE(intel);
+ LOCK(intel->bm);
bmSetFence(intel);
+ UNLOCK(intel->bm);
UNLOCK_HARDWARE(intel);
}
@@ -1350,7 +1357,12 @@ void bmFinishFence( struct intel_context
check_fenced(intel);
}
-
+void bmFinishFenceLock( struct intel_context *intel, unsigned fence )
+{
+ LOCK(intel->bm);
+ bmFinishFence(intel, fence);
+ UNLOCK(intel->bm);
+}
/* Specifically ignore texture memory sharing.
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index c8c5bf9..173d1d5 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -66,7 +66,7 @@ void intelCopyBuffer( const __DRIdrawabl
intelFlush( &intel->ctx );
- bmFinishFence(intel, intel->last_swap_fence);
+ bmFinishFenceLock(intel, intel->last_swap_fence);
/* The LOCK_HARDWARE is required for the cliprects. Buffer offsets
* should work regardless.
@@ -155,7 +155,7 @@ void intelCopyBuffer( const __DRIdrawabl
intel_batchbuffer_flush( intel->batch );
intel->second_last_swap_fence = intel->last_swap_fence;
- intel->last_swap_fence = bmSetFence( intel );
+ intel->last_swap_fence = bmSetFenceLock( intel );
UNLOCK_HARDWARE( intel );
if (!rect)
diff-tree de90bbd0b7c7b8569209770e9294fd967e10dac5 (from d214138910218a24e8ae427d5ec6ff886dcb98a8)
Author: Zou Nan hai <nanhai.zou at intel.com>
Date: Tue Dec 12 15:00:27 2006 +0800
fix for bug #99
diff --git a/src/mesa/drivers/dri/i965/brw_exec_api.c b/src/mesa/drivers/dri/i965/brw_exec_api.c
index 470fa6f..8b243c6 100644
--- a/src/mesa/drivers/dri/i965/brw_exec_api.c
+++ b/src/mesa/drivers/dri/i965/brw_exec_api.c
@@ -42,6 +42,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "dispatch.h"
#include "brw_exec.h"
+#include "intel_context.h"
+
static void reset_attrfv( struct brw_exec_context *exec );
@@ -522,6 +524,14 @@ static void GLAPIENTRY brw_exec_Begin( G
}
+static GLuint brw_max_prim( GLcontext *ctx )
+{
+ struct intel_context *intel = intel_context( ctx );
+ if (intel->numClipRects <= 1)
+ return BRW_MAX_PRIM;
+ return BRW_MAX_PRIM/intel->numClipRects;
+}
+
static void GLAPIENTRY brw_exec_End( void )
{
GET_CURRENT_CONTEXT( ctx );
@@ -536,7 +546,7 @@ static void GLAPIENTRY brw_exec_End( voi
ctx->Driver.CurrentExecPrimitive = GL_POLYGON+1;
- if (exec->vtx.prim_count == BRW_MAX_PRIM)
+ if (exec->vtx.prim_count >= brw_max_prim(ctx))
brw_exec_vtx_flush( exec );
}
else
diff-tree d214138910218a24e8ae427d5ec6ff886dcb98a8 (from parents)
Merge: 89433fef0dc9b7494904f99dd343042ddbbc3d80 26626c0052cd5442f609659aa9ed25ac78e65b55
Author: Eric Anholt <eric at anholt.net>
Date: Mon Dec 11 10:50:25 2006 -0800
Merge branch 'origin' into crestline
diff-tree 89433fef0dc9b7494904f99dd343042ddbbc3d80 (from b4d9c0048f036c3c6b7449ab2cd5b22e37a46a2d)
Author: Wang Zhenyu <zhenyu.z.wang at intel.com>
Date: Mon Dec 11 00:01:56 2006 -0800
ARB_occlusion_query support
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index 4707a70..e41042d 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -168,7 +168,7 @@ static void upload_wm_unit(struct brw_co
wm.wm5.line_stipple = 1;
}
- if (INTEL_DEBUG & DEBUG_STATS)
+ if (INTEL_DEBUG & DEBUG_STATS || intel->stats_wm)
wm.wm4.stats_enable = 1;
brw->wm.state_gs_offset = brw_cache_data( &brw->cache[BRW_WM_UNIT], &wm );
diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 5fc3d71..6bcc984 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -70,6 +70,7 @@ int INTEL_DEBUG = (0);
#define need_GL_ARB_vertex_buffer_object
#define need_GL_ARB_vertex_program
#define need_GL_ARB_window_pos
+#define need_GL_ARB_occlusion_query
#define need_GL_EXT_blend_color
#define need_GL_EXT_blend_equation_separate
#define need_GL_EXT_blend_func_separate
@@ -160,6 +161,7 @@ const struct dri_extension card_extensio
{ "GL_ARB_vertex_buffer_object", GL_ARB_vertex_buffer_object_functions },
{ "GL_ARB_vertex_program", GL_ARB_vertex_program_functions },
{ "GL_ARB_window_pos", GL_ARB_window_pos_functions },
+ { "GL_ARB_occlusion_query", GL_ARB_occlusion_query_functions},
{ "GL_EXT_blend_color", GL_EXT_blend_color_functions },
{ "GL_EXT_blend_equation_separate", GL_EXT_blend_equation_separate_functions },
{ "GL_EXT_blend_func_separate", GL_EXT_blend_func_separate_functions },
@@ -244,6 +246,36 @@ void intelFinish( GLcontext *ctx )
bmFinishFence(intel, bmLockAndFence(intel));
}
+static void
+intelBeginQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q)
+{
+ struct intel_context *intel = intel_context( ctx );
+ GLuint64EXT tmp = 0;
+ drmI830MMIO io = {
+ .read_write = MMIO_WRITE,
+ .reg = MMIO_REGS_PS_DEPTH_COUNT,
+ .data = &tmp
+ };
+ intel->stats_wm = GL_TRUE;
+ intelFinish(&intel->ctx);
+ drmCommandWrite(intel->driFd, DRM_I830_MMIO, &io, sizeof(io));
+}
+
+static void
+intelEndQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q)
+{
+ struct intel_context *intel = intel_context( ctx );
+ drmI830MMIO io = {
+ .read_write = MMIO_READ,
+ .reg = MMIO_REGS_PS_DEPTH_COUNT,
+ .data = &q->Result
+ };
+ intelFinish(&intel->ctx);
+ drmCommandRead(intel->driFd, DRM_I830_MMIO, &io, sizeof(io));
+ q->Ready = GL_TRUE;
+ intel->stats_wm = GL_FALSE;
+}
+
void intelInitDriverFunctions( struct dd_function_table *functions )
{
@@ -253,6 +285,8 @@ void intelInitDriverFunctions( struct dd
functions->Finish = intelFinish;
functions->GetString = intelGetString;
functions->UpdateState = intelInvalidateState;
+ functions->BeginQuery = intelBeginQuery;
+ functions->EndQuery = intelEndQuery;
/* CopyPixels can be accelerated even with the current memory
* manager:
diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index 85e574c..39eb775 100644
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -177,6 +177,7 @@ struct intel_context
GLuint second_last_swap_fence;
GLboolean aub_wrap;
+ GLboolean stats_wm;
struct intel_batchbuffer *batch;
diff --git a/src/mesa/drivers/dri/i965/server/i830_common.h b/src/mesa/drivers/dri/i965/server/i830_common.h
index e3bbdc7..f320378 100644
--- a/src/mesa/drivers/dri/i965/server/i830_common.h
+++ b/src/mesa/drivers/dri/i965/server/i830_common.h
@@ -52,6 +52,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#define DRM_I830_INIT_HEAP 0x0a
#define DRM_I830_CMDBUFFER 0x0b
#define DRM_I830_DESTROY_HEAP 0x0c
+#define DRM_I830_MMIO 0x10
typedef struct {
enum {
@@ -199,5 +200,23 @@ typedef struct {
int region;
} drmI830MemDestroyHeap;
+#define MMIO_READ 0
+#define MMIO_WRITE 1
+
+#define MMIO_REGS_IA_PRIMATIVES_COUNT 0
+#define MMIO_REGS_IA_VERTICES_COUNT 1
+#define MMIO_REGS_VS_INVOCATION_COUNT 2
+#define MMIO_REGS_GS_PRIMITIVES_COUNT 3
+#define MMIO_REGS_GS_INVOCATION_COUNT 4
+#define MMIO_REGS_CL_PRIMITIVES_COUNT 5
+#define MMIO_REGS_CL_INVOCATION_COUNT 6
+#define MMIO_REGS_PS_INVOCATION_COUNT 7
+#define MMIO_REGS_PS_DEPTH_COUNT 8
+
+typedef struct {
+ unsigned int read_write:1;
+ unsigned int reg:31;
+ void __user *data;
+} drmI830MMIO;
#endif /* _I830_DRM_H_ */
diff-tree b4d9c0048f036c3c6b7449ab2cd5b22e37a46a2d (from 9a94dae4c292bfc2aa94a3f86865550e2217b870)
Author: Wang Zhenyu <zhenyu.z.wang at intel.com>
Date: Mon Dec 11 00:00:51 2006 -0800
if (tex width < 4), mipmap calculation will be out of range
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 1353325..bf7047f 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -138,7 +138,7 @@ GLboolean brw_miptree_layout( struct int
/* Layout_below: step right after second mipmap.
*/
- if (level == mt->first_level + 1) {
+ if (level == mt->first_level + 1 && mt->pitch > 4) {
x += mt->pitch / 2;
x = (x + 3) & ~ 3;
}
diff-tree 9a94dae4c292bfc2aa94a3f86865550e2217b870 (from 183abbcd6b48178a3412ee8992131ce8c7e7b69d)
Author: Eric Anholt <eric at anholt.net>
Date: Wed Oct 18 00:24:01 2006 -0700
Avoid branch instructions while in single program flow mode.
There is an errata for Broadwater that threads don't have the instruction/loop
mask stacks initialized on thread spawn. In single program flow mode, those
stacks are not writable, so we can't initialize them. However, they do get
read during ELSE and ENDIF instructions. So, instead, replace branch
instructions in single program flow mode with predicated jumps (ADD to the ip
register), avoiding use of the more complicated branch instructions that may
fail. This is also a minor optimization as no ENDIF equivalent is necessary.
diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c
index 0e8591a..3bec153 100644
--- a/src/mesa/drivers/dri/i965/brw_clip.c
+++ b/src/mesa/drivers/dri/i965/brw_clip.c
@@ -62,6 +62,8 @@ static void compile_clip_prog( struct br
*/
brw_init_compile(&c.func);
+ c.func.single_program_flow = 1;
+
c.key = *key;
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 1afa0f8..d4dbcf3 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -104,6 +104,7 @@ struct brw_compile {
struct brw_instruction *current;
GLuint flag_value;
+ GLboolean single_program_flow;
};
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 6425c91..9992b47 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -464,7 +464,6 @@ struct brw_instruction *brw_JMPI(struct
return insn;
}
-
/* EU takes the value from the flag register and pushes it onto some
* sort of a stack (presumably merging with any flag value already on
* the stack). Within an if block, the flags at the top of the stack
@@ -482,7 +481,16 @@ struct brw_instruction *brw_JMPI(struct
*/
struct brw_instruction *brw_IF(struct brw_compile *p, GLuint execute_size)
{
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_IF);
+ struct brw_instruction *insn;
+
+ if (p->single_program_flow) {
+ assert(execute_size == BRW_EXECUTE_1);
+
+ insn = next_insn(p, BRW_OPCODE_ADD);
+ insn->header.predicate_inverse = 1;
+ } else {
+ insn = next_insn(p, BRW_OPCODE_IF);
+ }
/* Override the defaults for this instruction:
*/
@@ -504,7 +512,13 @@ struct brw_instruction *brw_IF(struct br
struct brw_instruction *brw_ELSE(struct brw_compile *p,
struct brw_instruction *if_insn)
{
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_ELSE);
+ struct brw_instruction *insn;
+
+ if (p->single_program_flow) {
+ insn = next_insn(p, BRW_OPCODE_ADD);
+ } else {
+ insn = next_insn(p, BRW_OPCODE_ELSE);
+ }
brw_set_dest(insn, brw_ip_reg());
brw_set_src0(insn, brw_ip_reg());
@@ -516,11 +530,17 @@ struct brw_instruction *brw_ELSE(struct
/* Patch the if instruction to point at this instruction.
*/
- assert(if_insn->header.opcode == BRW_OPCODE_IF);
+ if (p->single_program_flow) {
+ assert(if_insn->header.opcode == BRW_OPCODE_ADD);
- if_insn->bits3.if_else.jump_count = insn - if_insn;
- if_insn->bits3.if_else.pop_count = 1;
- if_insn->bits3.if_else.pad0 = 0;
+ if_insn->bits3.ud = (insn - if_insn + 1) * 16;
+ } else {
+ assert(if_insn->header.opcode == BRW_OPCODE_IF);
+
+ if_insn->bits3.if_else.jump_count = insn - if_insn;
+ if_insn->bits3.if_else.pop_count = 1;
+ if_insn->bits3.if_else.pad0 = 0;
+ }
return insn;
}
@@ -528,63 +548,76 @@ struct brw_instruction *brw_ELSE(struct
void brw_ENDIF(struct brw_compile *p,
struct brw_instruction *patch_insn)
{
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_ENDIF);
+ if (p->single_program_flow) {
+ /* In single program flow mode, there's no need to execute an ENDIF,
+ * since we don't need to do any stack operations, and if we're executing
+ * currently, we want to just continue executing.
+ */
+ struct brw_instruction *next = &p->store[p->nr_insn];
- brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
- brw_set_src0(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
- brw_set_src1(insn, brw_imm_d(0x0));
+ assert(patch_insn->header.opcode == BRW_OPCODE_ADD);
- insn->header.compression_control = BRW_COMPRESSION_NONE;
- insn->header.execution_size = patch_insn->header.execution_size;
- insn->header.mask_control = BRW_MASK_ENABLE;
+ patch_insn->bits3.ud = (next - patch_insn) * 16;
+ } else {
+ struct brw_instruction *insn = next_insn(p, BRW_OPCODE_ENDIF);
- assert(patch_insn->bits3.if_else.jump_count == 0);
-
- /* Patch the if or else instructions to point at this or the next
- * instruction respectively.
- */
- if (patch_insn->header.opcode == BRW_OPCODE_IF) {
- /* Automagically turn it into an IFF:
+ brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
+ brw_set_src0(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
+ brw_set_src1(insn, brw_imm_d(0x0));
+
+ insn->header.compression_control = BRW_COMPRESSION_NONE;
+ insn->header.execution_size = patch_insn->header.execution_size;
+ insn->header.mask_control = BRW_MASK_ENABLE;
+
+ assert(patch_insn->bits3.if_else.jump_count == 0);
+
+ /* Patch the if or else instructions to point at this or the next
+ * instruction respectively.
*/
- patch_insn->header.opcode = BRW_OPCODE_IFF;
- patch_insn->bits3.if_else.jump_count = insn - patch_insn + 1;
- patch_insn->bits3.if_else.pop_count = 0;
- patch_insn->bits3.if_else.pad0 = 0;
+ if (patch_insn->header.opcode == BRW_OPCODE_IF) {
+ /* Automagically turn it into an IFF:
+ */
+ patch_insn->header.opcode = BRW_OPCODE_IFF;
+ patch_insn->bits3.if_else.jump_count = insn - patch_insn + 1;
+ patch_insn->bits3.if_else.pop_count = 0;
+ patch_insn->bits3.if_else.pad0 = 0;
+ } else if (patch_insn->header.opcode == BRW_OPCODE_ELSE) {
+ patch_insn->bits3.if_else.jump_count = insn - patch_insn + 1;
+ patch_insn->bits3.if_else.pop_count = 1;
+ patch_insn->bits3.if_else.pad0 = 0;
+ } else {
+ assert(0);
+ }
+ /* Also pop item off the stack in the endif instruction:
+ */
+ insn->bits3.if_else.jump_count = 0;
+ insn->bits3.if_else.pop_count = 1;
+ insn->bits3.if_else.pad0 = 0;
}
- else if (patch_insn->header.opcode == BRW_OPCODE_ELSE) {
- patch_insn->bits3.if_else.jump_count = insn - patch_insn + 1;
- patch_insn->bits3.if_else.pop_count = 1;
- patch_insn->bits3.if_else.pad0 = 0;
- }
- else {
- assert(0);
- }
-
- /* Also pop item off the stack in the endif instruction:
- */
- insn->bits3.if_else.jump_count = 0;
- insn->bits3.if_else.pop_count = 1;
- insn->bits3.if_else.pad0 = 0;
}
/* DO/WHILE loop:
*/
struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size)
{
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_DO);
+ if (p->single_program_flow) {
+ return &p->store[p->nr_insn];
+ } else {
+ struct brw_instruction *insn = next_insn(p, BRW_OPCODE_DO);
- /* Override the defaults for this instruction:
- */
- brw_set_dest(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
- brw_set_src0(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
- brw_set_src1(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
+ /* Override the defaults for this instruction:
+ */
+ brw_set_dest(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
+ brw_set_src0(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
+ brw_set_src1(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
- insn->header.compression_control = BRW_COMPRESSION_NONE;
- insn->header.execution_size = execute_size;
-/* insn->header.mask_control = BRW_MASK_ENABLE; */
+ insn->header.compression_control = BRW_COMPRESSION_NONE;
+ insn->header.execution_size = execute_size;
+ /* insn->header.mask_control = BRW_MASK_ENABLE; */
- return insn;
+ return insn;
+ }
}
@@ -592,19 +625,31 @@ struct brw_instruction *brw_DO(struct br
void brw_WHILE(struct brw_compile *p,
struct brw_instruction *do_insn)
{
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_WHILE);
+ struct brw_instruction *insn;
+
+ if (p->single_program_flow)
+ insn = next_insn(p, BRW_OPCODE_ADD);
+ else
+ insn = next_insn(p, BRW_OPCODE_WHILE);
brw_set_dest(insn, brw_ip_reg());
brw_set_src0(insn, brw_ip_reg());
brw_set_src1(insn, brw_imm_d(0x0));
insn->header.compression_control = BRW_COMPRESSION_NONE;
- insn->header.execution_size = do_insn->header.execution_size;
- assert(do_insn->header.opcode == BRW_OPCODE_DO);
- insn->bits3.if_else.jump_count = do_insn - insn;
- insn->bits3.if_else.pop_count = 0;
- insn->bits3.if_else.pad0 = 0;
+ if (p->single_program_flow) {
+ insn->header.execution_size = BRW_EXECUTE_1;
+
+ insn->bits3.d = (do_insn - insn) * 16;
+ } else {
+ insn->header.execution_size = do_insn->header.execution_size;
+
+ assert(do_insn->header.opcode == BRW_OPCODE_DO);
+ insn->bits3.if_else.jump_count = do_insn - insn;
+ insn->bits3.if_else.pop_count = 0;
+ insn->bits3.if_else.pad0 = 0;
+ }
/* insn->header.mask_control = BRW_MASK_ENABLE; */
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
index 7d3f9dd..9066e42 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -66,7 +66,9 @@ static void compile_gs_prog( struct brw_
/* Begin the compilation:
*/
brw_init_compile(&c.func);
-
+
+ c.func.single_program_flow = 1;
+
/* For some reason the thread is spawned with only 4 channels
* unmasked.
*/
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index 25acdcf..10fee94 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -519,7 +519,22 @@ struct thread3
struct brw_clip_unit_state
{
struct thread0 thread0;
- struct thread1 thread1;
+ struct
+ {
+ GLuint pad0:7;
+ GLuint sw_exception_enable:1;
+ GLuint pad1:3;
+ GLuint mask_stack_exception_enable:1;
+ GLuint pad2:1;
+ GLuint illegal_op_exception_enable:1;
+ GLuint pad3:2;
+ GLuint floating_point_mode:1;
+ GLuint thread_priority:1;
+ GLuint binding_table_entry_count:8;
+ GLuint pad4:5;
+ GLuint single_program_flow:1;
+ } thread1;
+
struct thread2 thread2;
struct thread3 thread3;
@@ -532,8 +547,8 @@ struct brw_clip_unit_state
GLuint pad1:1;
GLuint urb_entry_allocation_size:5;
GLuint pad2:1;
- GLuint max_threads:6; /* may be less */
- GLuint pad3:1;
+ GLuint max_threads:1; /* may be less */
+ GLuint pad3:6;
} thread4;
struct
@@ -1322,6 +1337,7 @@ struct brw_instruction
GLuint end_of_thread:1;
} generic;
+ GLint d;
GLuint ud;
} bits3;
};
diff-tree 183abbcd6b48178a3412ee8992131ce8c7e7b69d (from 05362682672f5edbd57437fa29c3d5d7d2ad7aba)
Author: Eric Anholt <eric at anholt.net>
Date: Wed Oct 11 12:16:09 2006 -0700
Connect INTEL_DEBUG=sync up to cmd/batch ioctls.
diff --git a/src/mesa/drivers/dri/i965/intel_ioctl.c b/src/mesa/drivers/dri/i965/intel_ioctl.c
index d1f2e3f..d8176c5 100644
--- a/src/mesa/drivers/dri/i965/intel_ioctl.c
+++ b/src/mesa/drivers/dri/i965/intel_ioctl.c
@@ -43,6 +43,26 @@
#include "drm.h"
#include "bufmgr.h"
+static int intelWaitIdleLocked( struct intel_context *intel )
+{
+ static int in_wait_idle = 0;
+ unsigned int fence;
+
+ if (!in_wait_idle) {
+ if (INTEL_DEBUG & DEBUG_SYNC) {
+ fprintf(stderr, "waiting for idle\n");
+ }
+
+ in_wait_idle = 1;
+ fence = bmSetFence(intel);
+ intelWaitIrq(intel, fence);
+ in_wait_idle = 0;
+
+ return bmTestFence(intel, fence);
+ } else {
+ return 1;
+ }
+}
int intelEmitIrqLocked( struct intel_context *intel )
{
@@ -139,7 +159,11 @@ void intel_batch_ioctl( struct intel_con
UNLOCK_HARDWARE(intel);
exit(1);
}
- }
+
+ if (INTEL_DEBUG & DEBUG_SYNC) {
+ intelWaitIdleLocked(intel);
+ }
+ }
}
void intel_cmd_ioctl( struct intel_context *intel,
@@ -171,5 +195,9 @@ void intel_cmd_ioctl( struct intel_conte
UNLOCK_HARDWARE(intel);
exit(1);
}
- }
+
+ if (INTEL_DEBUG & DEBUG_SYNC) {
+ intelWaitIdleLocked(intel);
+ }
+ }
}
diff-tree 05362682672f5edbd57437fa29c3d5d7d2ad7aba (from eb9033c72362ac217ef1d38d428a61e473ddd507)
Author: Wang Zhenyu <zhenyu.z.wang at intel.com>
Date: Tue Aug 22 23:29:03 2006 +0800
adding pci id of Crestline
diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index d13e287..5fc3d71 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -117,6 +117,9 @@ static const GLubyte *intelGetString( GL
case PCI_CHIP_I946_GZ:
chipset = "Intel(R) 946GZ"; break;
break;
+ case PCI_CHIP_CRESTLINE:
+ chipset = "Intel(R) Crestline"; break;
+ break;
default:
chipset = "Unknown Intel Chipset"; break;
}
diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index 8367a95..85e574c 100644
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -383,6 +383,7 @@ extern int INTEL_DEBUG;
#define PCI_CHIP_I965_Q 0x2992
#define PCI_CHIP_I965_G_1 0x2982
#define PCI_CHIP_I946_GZ 0x2972
+#define PCI_CHIP_CRESTLINE 0x2A02
/* ================================================================
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