mesa: Changes to 'master'

[Eric Anholt]

 configs/freebsd-dri                            |    8 -
 src/mesa/drivers/dri/i915/i915_reg.h           |    2 
 src/mesa/drivers/dri/i915/intel_batchbuffer.c  |    2 
 src/mesa/drivers/dri/i915/intel_blit.c         |   18 +---
 src/mesa/drivers/dri/i915/intel_context.h      |    5 -
 src/mesa/drivers/dri/i915/intel_reg.h          |   88 --------------------
 src/mesa/drivers/dri/i965/brw_clip_state.c     |    3 
 src/mesa/drivers/dri/i965/brw_curbe.c          |    2 
 src/mesa/drivers/dri/i965/brw_draw_upload.c    |   10 +-
 src/mesa/drivers/dri/i965/brw_gs_state.c       |    3 
 src/mesa/drivers/dri/i965/brw_sf_state.c       |    2 
 src/mesa/drivers/dri/i965/brw_state_cache.c    |    2 
 src/mesa/drivers/dri/i965/brw_state_pool.c     |    5 -
 src/mesa/drivers/dri/i965/brw_tex_layout.c     |    4 
 src/mesa/drivers/dri/i965/brw_vs_state.c       |    2 
 src/mesa/drivers/dri/i965/brw_wm_state.c       |    4 
 src/mesa/drivers/dri/i965/bufmgr_fake.c        |    2 
 src/mesa/drivers/dri/i965/intel_batchbuffer.c  |    4 
 src/mesa/drivers/dri/i965/intel_batchbuffer.h  |    6 +
 src/mesa/drivers/dri/i965/intel_blit.c         |  108 +++++++++++--------------
 src/mesa/drivers/dri/i965/intel_context.h      |    2 
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c  |    4 
 src/mesa/drivers/dri/i965/intel_pixel_bitmap.c |    9 --
 src/mesa/drivers/dri/i965/intel_reg.h          |   91 ---------------------
 src/mesa/drivers/dri/intel/intel_reg.h         |   76 +++++++++++++++++
 src/mesa/drivers/dri/intel/intel_tex_layout.c  |   20 +---
 26 files changed, 180 insertions(+), 302 deletions(-)

commit diffs at http://gitweb.freedesktop.org/?p=mesa/mesa.git;a=summary

New commits:
commit 77e0523fb7769df4bf43747e136b1653b2421b97
Author: Eric Anholt <eric at anholt.net>
Date:   Thu Oct 4 12:07:25 2007 -0700

    [965] Replace various alignment code with a shared ALIGN() macro.
    
    In the process, fix some alignment issues:
    - Scratch space allocation was aligned into units of 1KB, while the allocation
      wanted units of bytes, so we never allocated enough space for scratch.
    - GRF register count was programmed as ALIGN(val - 1, 16) / 16 instead of
      ALIGN(val, 16) / 16 - 1, which overcounted for val != 16n+1.

commit 0fc9efd8f0b1b6c4e3525a50e3478e5aef72531a
Author: Eric Anholt <eric at anholt.net>
Date:   Thu Oct 4 11:16:50 2007 -0700

    Replace bmBufferOffset usage in batchbuffer setup with OUT_RELOC.
    
    This is in preparation for 965 TTM.

commit 6bac9478c39fbe7955d10a21a2d7743697427a56
Author: Eric Anholt <eric at anholt.net>
Date:   Wed Oct 3 16:59:01 2007 -0700

    Replace duplicated intel_reg.h with a shared header.

commit 1f7378ee465eba8d82d224a7bf835e38c5ab6ee2
Author: Eric Anholt <eric at anholt.net>
Date:   Wed Oct 3 16:30:42 2007 -0700

    Replace some structure-based batch preparation with plain OUT_BATCH.
    
    OUT_BATCH is far more amenable to the upcoming relocations being done for TTM
    support.

commit ffa94e5b1e5537576ce5e910430116ec3e705457
Author: Eric Anholt <eric at anholt.net>
Date:   Fri Sep 28 13:51:13 2007 -0700

    FreeBSD: more /usr/X11R6->/usr/local