mesa: Changes to 'drm-gem'

[Eric Anholt]

The branch, drm-gem has been updated
        Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=drm-gem

Summary of changes:
 src/mesa/drivers/dri/intel/intel_context.c |    3 +
 src/mesa/drivers/dri/intel/intel_context.h |    1 +
 src/mesa/drivers/dri/intel/intel_fbo.c     |   13 ++++-
 src/mesa/drivers/dri/intel/intel_fbo.h     |    7 ++-
 src/mesa/drivers/dri/intel/intel_screen.c  |   48 ++++++++++++++------
 src/mesa/drivers/dri/intel/intel_screen.h  |    6 +++
 src/mesa/drivers/dri/intel/intel_span.c    |   68 +++++++++++++++++++--------
 src/mesa/drivers/dri/intel/intel_span.h    |    7 +--
 8 files changed, 108 insertions(+), 45 deletions(-)

       via  4b3ed4d2d16811a624857519e95303017f4160b5 (commit)
       via  19f585a3cf65887e249d630fe43e83e7e7618dfa (commit)
       via  e74f54793e45dd2e36474f6fc527456647f32efd (commit)
      from  f059a3302260075e9cfd35649dc3877726291d8d (commit)


- Commits -----------------------------------------------
commit 4b3ed4d2d16811a624857519e95303017f4160b5
Author: Eric Anholt <eric at anholt.net>
Date:   Wed Jul 2 10:21:44 2008 -0700

    intel-gem: Fix y-tile swizzling for our G965 with swizzle_mode=1.
    
    Apparently in Y mode we get bit 6 ^ bit 9.  The reflect demo in 'd' mode now
    displays correctly.

commit 19f585a3cf65887e249d630fe43e83e7e7618dfa
Author: Eric Anholt <eric at anholt.net>
Date:   Wed Jul 2 09:10:21 2008 -0700

    intel-gem: Fix Y-tiling span setup.
    
    The boolean that the server gives us for whether the region is tiled was
    getting used as the enum for what tiling mode.  Instead, guess the correct
    tiling in screen setup.
    
    Also, fix the Y-tiling pitch setup.  The pitch to the next tile in Y is
    32 scanlines, not 8.

commit e74f54793e45dd2e36474f6fc527456647f32efd
Author: Eric Anholt <eric at anholt.net>
Date:   Tue Jul 1 15:09:24 2008 -0700

    intel-gem: Move bit 6 x tiling swizzle to a driconf option, and add new mode.
    
    It turns out that it's not just deviceID dependent, and there's some additional
    undefined factor that determines the bit 6 swizzling.  It's now controllable
    with swizzle_mode=[012] until we get a response on how to automatically detect.

---------------------------------