mesa: Changes to 'mesa_7_0_branch'
Haihao Xiang
haihao at kemper.freedesktop.org
Mon Jun 2 07:14:38 UTC 2008
The branch, mesa_7_0_branch has been updated
Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=mesa_7_0_branch
Summary of changes:
src/mesa/drivers/dri/i915/i915_fragprog.c | 2 +-
src/mesa/drivers/dri/i965/brw_clip_unfilled.c | 4 +-
src/mesa/drivers/dri/i965/brw_draw_upload.c | 25 +++++++++++++++++++
src/mesa/drivers/dri/i965/brw_eu_emit.c | 2 +-
src/mesa/drivers/dri/i965/brw_vs_tnl.c | 8 +++++-
src/mesa/drivers/dri/i965/brw_wm.c | 2 +-
src/mesa/drivers/dri/i965/brw_wm_fp.c | 2 +-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 11 ++++++--
src/mesa/drivers/dri/i965/intel_pixel_bitmap.c | 29 +++++++++++----------
src/mesa/main/depthstencil.c | 2 +-
src/mesa/x86/read_rgba_span_x86.S | 4 ++-
11 files changed, 65 insertions(+), 26 deletions(-)
via 6f851d88758c2157d25751b9e2b5309b221faea7 (commit)
via 9b99bf89c40e5b819e7e8a090b5cf7ca83bf1944 (commit)
via 7346fca083cc59a52b5168b539d848b10af8bd34 (commit)
via 7facbb69c6b308719dad7121adb1caaef0ea7932 (commit)
via f59267d650961ea536bf790cce905747202cca6d (commit)
via 71cb014195d11d0cdee4817e52c475397d955d94 (commit)
via 6c0f8db9c25f4d0e44e748b8a45a2b6a92764b39 (commit)
via 49f1e2fc4c738f123d654b466fc7beac0cff5007 (commit)
via 2d26e195353a7f45c094a719e8a7b8ef28e74d8e (commit)
via 5b0c6cd49a8b73afe466beee3f33ba231b658ab2 (commit)
via c3ee8e46ccd6a011fe38c005ad84da8e51c4e7dd (commit)
via 46aac242612b8570ec7d309b2835c5d6cdafa4b0 (commit)
via e1032ce7182ad01ee4053a99ef1a7358954c0495 (commit)
from ce636f36f293a137dc7f129afec464bfbc95eb4e (commit)
- Commits -----------------------------------------------
commit 6f851d88758c2157d25751b9e2b5309b221faea7
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Wed May 14 09:52:46 2008 +0800
_generic_read_RGBA_span_BGRA8888_REV_SSE2: It should adjust the source
and target pointers after do the first 2 pixels. fix bug #15850
Cherry-picked from commit 4b7d301c94d33394550322768a9d2232087b2d64
commit 9b99bf89c40e5b819e7e8a090b5cf7ca83bf1944
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Fri Mar 28 17:32:45 2008 +0800
i965: depth offset on glPolygonMode(GL_LINE/GL_POINT)
Cherry picked from 184cf464f4183a664fa0358fe118735e6fd98afe
commit 7346fca083cc59a52b5168b539d848b10af8bd34
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Mon Jun 2 14:15:24 2008 +0800
965: use RGB565 to render a bitmap if Depth is 16
Cherry-picked from commit 5982d397990fd2ae4c729977cf8d22da5ef29987.
commit 7facbb69c6b308719dad7121adb1caaef0ea7932
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Fri Feb 15 16:13:11 2008 +0800
i965: don't swizzle fogcoord if FogOption is FOG_NONE.
fix #10788 issue on 965.
Cherry picked from commit 83068115e2104b1880431ada96fa37e632149a86
commit f59267d650961ea536bf790cce905747202cca6d
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Mon Jun 2 14:06:14 2008 +0800
i915: set fogcoord to (f,0,0,1). fix #10788 issue on 915.
Cherry picked from commit 7eef52e975e852207ee840c74cd822c8f8c90a01
commit 71cb014195d11d0cdee4817e52c475397d955d94
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Tue Dec 25 14:16:05 2007 +0800
mesa: fix a bad cast in put_values_z24.
The values passed to put_values_z24 are GLuint,
not GLubyte. fix #13543
Cherry picked from commit cf46aee14a9df86ce336823fd02da650e262f77e
commit 6c0f8db9c25f4d0e44e748b8a45a2b6a92764b39
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Tue Nov 27 09:45:32 2007 +0800
i965: The jump instruction count is added
to IP pre-increment, and should point to
the first instruction after the do instruction
of the do-while block of code
Cherry picked from commit 46e03d584a18b89fef956fed3d52e15775846250
commit 49f1e2fc4c738f123d654b466fc7beac0cff5007
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Thu Sep 20 17:42:13 2007 +0800
i965: fix an error in brw_vs_tnl.c
Update the tnl program if the state of TEXMAT is changed.
commit 2d26e195353a7f45c094a719e8a7b8ef28e74d8e
Author: Eric Anholt <eric at anholt.net>
Date: Tue Jan 8 16:20:28 2008 -0800
[965] Clarify a bit of index buffer upload code.
Cherry picked from commit 5a49e84fcd858a1ad9c0ad839ccbe93504593cd0
commit 5b0c6cd49a8b73afe466beee3f33ba231b658ab2
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Fri Sep 14 11:10:23 2007 +0800
i965: align the address of the first element within
the index buffer. (fix#11910)
Cherry picked from ea07a0df9a2f689b8f5acaf92c40bbbd602cab3c
commit c3ee8e46ccd6a011fe38c005ad84da8e51c4e7dd
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Mon Aug 13 17:16:27 2007 +0800
i965: fix projtex_mask
projtex_mask is only an 8bit field, and wm.input_size_masks includes
other attributes' information, therefore right shift is needed.
Cherry picked from 88451b04e9cd39db9cc9315aaf69e074614f22f9
commit 46aac242612b8570ec7d309b2835c5d6cdafa4b0
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Tue Jul 31 22:40:42 2007 +0800
i965: fix bad casts in do_blit_bitmap to support WindowPos correctly
Cherry picked from commit e66757c8babe6968ea2e506d1214c8063cbd0760
commit e1032ce7182ad01ee4053a99ef1a7358954c0495
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Mon Jun 2 11:48:41 2008 +0800
i965: fix DEPTH_TEXTURE_MODE
Cherry picked from commit 6e620162a1b235ade227368b87fa993e844d7077 with
manual changes
---------------------------------
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