Mesa (master): i965: Allocate destination registers for GLSL TEX instructions contiguously.
Eric Anholt
anholt at kemper.freedesktop.org
Wed Aug 12 20:20:51 UTC 2009
Module: Mesa
Branch: master
Commit: 5faa0dc591527683e32306456cbfe6d93afa04da
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5faa0dc591527683e32306456cbfe6d93afa04da
Author: Eric Anholt <eric at anholt.net>
Date: Wed Aug 12 13:17:15 2009 -0700
i965: Allocate destination registers for GLSL TEX instructions contiguously.
This matches brw_wm_pass*.c behavior, and fixes the norsetto shadow demo.
Bug #19489
---
src/mesa/drivers/dri/i965/brw_wm_glsl.c | 24 ++++++++++++++++++++++++
1 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
index 26fe40c..a5b18ec 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
@@ -10,6 +10,9 @@ enum _subroutine {
SUB_NOISE1, SUB_NOISE2, SUB_NOISE3, SUB_NOISE4
};
+static struct brw_reg get_dst_reg(struct brw_wm_compile *c,
+ const struct prog_instruction *inst,
+ GLuint component);
/**
* Determine if the given fragment program uses GLSL features such
@@ -390,6 +393,27 @@ static void prealloc_reg(struct brw_wm_compile *c)
prealloc_grf(c, 126);
prealloc_grf(c, 127);
+ for (i = 0; i < c->nr_fp_insns; i++) {
+ const struct prog_instruction *inst = &c->prog_instructions[i];
+ struct brw_reg dst[4];
+
+ switch (inst->Opcode) {
+ case OPCODE_TEX:
+ case OPCODE_TXB:
+ /* Allocate the channels of texture results contiguously,
+ * since they are written out that way by the sampler unit.
+ */
+ for (j = 0; j < 4; j++) {
+ dst[j] = get_dst_reg(c, inst, j);
+ if (j != 0)
+ assert(dst[j].nr == dst[j - 1].nr + 1);
+ }
+ break;
+ default:
+ break;
+ }
+ }
+
/* An instruction may reference up to three constants.
* They'll be found in these registers.
* XXX alloc these on demand!
More information about the mesa-commit
mailing list