Mesa (master): r600: remove unused offset_mod stuff
Alex Deucher
agd5f at kemper.freedesktop.org
Fri Jul 31 19:00:57 UTC 2009
Module: Mesa
Branch: master
Commit: 177c33c481d84058f57e761b25cba735b9c7e6ea
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=177c33c481d84058f57e761b25cba735b9c7e6ea
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Fri Jul 31 12:06:26 2009 -0400
r600: remove unused offset_mod stuff
this is a step in migrating to the common cs code
---
src/mesa/drivers/dri/r600/r600_cmdbuf.c | 27 +----------------
src/mesa/drivers/dri/r600/r600_cmdbuf.h | 8 ++---
src/mesa/drivers/dri/r600/r600_context.h | 7 ----
src/mesa/drivers/dri/r600/r700_chip.c | 44 +++++-----------------------
src/mesa/drivers/dri/r600/r700_render.c | 7 +----
src/mesa/drivers/dri/r600/r700_vertprog.c | 2 -
6 files changed, 14 insertions(+), 81 deletions(-)
diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c
index 15b9992..d2e75c0 100644
--- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c
+++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c
@@ -78,8 +78,7 @@ int r600_cs_write_reloc(struct radeon_cs *cs,
struct radeon_bo *bo,
uint32_t read_domain,
uint32_t write_domain,
- uint32_t flags,
- offset_modifiers* poffset_mod)
+ uint32_t flags)
{
struct r600_cs_reloc_legacy *relocs;
int i;
@@ -135,10 +134,6 @@ int r600_cs_write_reloc(struct radeon_cs *cs,
cs->section_ndw += 2;
cs->section_cdw += 2;
- relocs[i].offset_mod.shift = poffset_mod->shift;
- relocs[i].offset_mod.shiftbits = poffset_mod->shiftbits;
- relocs[i].offset_mod.mask = poffset_mod->mask;
-
return 0;
}
}
@@ -160,9 +155,6 @@ int r600_cs_write_reloc(struct radeon_cs *cs,
{
return -ENOMEM;
}
- relocs[cs->crelocs].offset_mod.shift = poffset_mod->shift;
- relocs[cs->crelocs].offset_mod.shiftbits = poffset_mod->shiftbits;
- relocs[cs->crelocs].offset_mod.mask = poffset_mod->mask;
relocs[cs->crelocs].indices[0] = cs->cdw - 1;
relocs[cs->crelocs].reloc_indices[0] = cs->section_cdw;
@@ -286,28 +278,13 @@ restart:
exit(0);
return -EINVAL;
}
- /* apply offset operator */
- switch (relocs[i].offset_mod.shift)
- {
- case NO_SHIFT:
- asicoffset = asicoffset & relocs[i].offset_mod.mask;
- break;
- case LEFT_SHIFT:
- asicoffset = (asicoffset << relocs[i].offset_mod.shiftbits) & relocs[i].offset_mod.mask;
- break;
- case RIGHT_SHIFT:
- asicoffset = (asicoffset >> relocs[i].offset_mod.shiftbits) & relocs[i].offset_mod.mask;
- break;
- default:
- break;
- };
/* pkt3 nop header in ib chunk */
cs->packets[relocs[i].reloc_indices[j]] = 0xC0001000;
/* reloc index in ib chunk */
cs->packets[relocs[i].reloc_indices[j] + 1] = offset_dw;
-
+
/* asic offset in reloc chunk */ /* see alex drm r600_nomm_relocate */
reloc_chunk[offset_dw] = asicoffset;
reloc_chunk[offset_dw + 3] = 0;
diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.h b/src/mesa/drivers/dri/r600/r600_cmdbuf.h
index bd1ed7f..5df0cf1 100644
--- a/src/mesa/drivers/dri/r600/r600_cmdbuf.h
+++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.h
@@ -132,15 +132,13 @@ struct r600_cs_reloc_legacy {
uint32_t cindices;
uint32_t *indices;
uint32_t *reloc_indices;
- struct offset_modifiers offset_mod;
};
extern int r600_cs_write_reloc(struct radeon_cs *cs,
struct radeon_bo *bo,
uint32_t read_domain,
uint32_t write_domain,
- uint32_t flags,
- offset_modifiers* poffset_mod);
+ uint32_t flags);
static inline void r600_cs_write_dword(struct radeon_cs *cs, uint32_t dword)
{
@@ -171,7 +169,7 @@ struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_cont
/**
* Write a relocated dword to the command buffer.
*/
-#define R600_OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags, offset_mod) \
+#define R600_OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags) \
do { \
if (0 && offset) { \
fprintf(stderr, "(%s:%s:%d) offset : %d\n", \
@@ -179,7 +177,7 @@ struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_cont
} \
r600_cs_write_dword(b_l_rmesa->cmdbuf.cs, offset); \
r600_cs_write_reloc(b_l_rmesa->cmdbuf.cs, \
- bo, rd, wd, flags, offset_mod); \
+ bo, rd, wd, flags); \
} while(0)
/* R600/R700 */
diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h
index bcb33e1..fbb8164 100644
--- a/src/mesa/drivers/dri/r600/r600_context.h
+++ b/src/mesa/drivers/dri/r600/r600_context.h
@@ -128,13 +128,6 @@ enum
RIGHT_SHIFT = 2,
};
-typedef struct offset_modifiers
-{
- GLuint shift;
- GLuint shiftbits;
- GLuint mask;
-} offset_modifiers;
-
/**
* \brief R600 context structure.
*/
diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index f6face5..ad4f29b 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -247,7 +247,6 @@ GLboolean r700SendTextureState(context_t *context)
{
unsigned int i;
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- offset_modifiers offset_mod = {NO_SHIFT, 0, 0xFFFFFFFF};
struct radeon_bo *bo = NULL;
BATCH_LOCALS(&context->radeon);
@@ -272,11 +271,11 @@ GLboolean r700SendTextureState(context_t *context)
R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
bo,
0,
- RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod);
+ RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
bo,
r700->textures[i]->SQ_TEX_RESOURCE3,
- RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod);
+ RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
@@ -314,8 +313,6 @@ void r700SetupVTXConstants(GLcontext * ctx,
{
context_t *context = R700_CONTEXT(ctx);
struct radeon_aos * paos = (struct radeon_aos *)pAos;
- offset_modifiers offset_mod = {NO_SHIFT, 0, 0xFFFFFFFF};
-
BATCH_LOCALS(&context->radeon);
unsigned int uSQ_VTX_CONSTANT_WORD0_0;
@@ -357,7 +354,7 @@ void r700SetupVTXConstants(GLcontext * ctx,
R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
paos->bo,
uSQ_VTX_CONSTANT_WORD0_0,
- RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod);
+ RADEON_GEM_DOMAIN_GTT, 0, 0);
R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
@@ -483,7 +480,6 @@ GLboolean r700SendDepthTargetState(context_t *context)
{
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
struct radeon_renderbuffer *rrb;
- offset_modifiers offset_mod;
BATCH_LOCALS(&context->radeon);
rrb = radeon_get_depthbuffer(&context->radeon);
@@ -492,10 +488,6 @@ GLboolean r700SendDepthTargetState(context_t *context)
return GL_FALSE;
}
- offset_mod.shift = NO_SHIFT;
- offset_mod.shiftbits = 0;
- offset_mod.mask = 0xFFFFFFFF;
-
BEGIN_BATCH_NO_AUTOSTATE(9);
R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2);
R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All);
@@ -504,7 +496,7 @@ GLboolean r700SendDepthTargetState(context_t *context)
R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All,
rrb->bo,
r700->DB_DEPTH_BASE.u32All,
- 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod);
+ 0, RADEON_GEM_DOMAIN_VRAM, 0);
R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
R600_OUT_BATCH(r700->DB_HTILE_DATA_BASE.u32All);
END_BATCH();
@@ -541,7 +533,6 @@ GLboolean r700SendRenderTargetState(context_t *context, int id)
{
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
struct radeon_renderbuffer *rrb;
- offset_modifiers offset_mod;
BATCH_LOCALS(&context->radeon);
rrb = radeon_get_colorbuffer(&context->radeon);
@@ -556,16 +547,12 @@ GLboolean r700SendRenderTargetState(context_t *context, int id)
if (!r700->render_target[id].enabled)
return GL_FALSE;
- offset_mod.shift = NO_SHIFT;
- offset_mod.shiftbits = 0;
- offset_mod.mask = 0xFFFFFFFF;
-
BEGIN_BATCH_NO_AUTOSTATE(3);
R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1);
R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All,
rrb->bo,
r700->render_target[id].CB_COLOR0_BASE.u32All,
- 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod);
+ 0, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
@@ -603,15 +590,10 @@ GLboolean r700SendPSState(context_t *context)
{
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
struct radeon_bo * pbo;
- offset_modifiers offset_mod;
BATCH_LOCALS(&context->radeon);
pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context));
- offset_mod.shift = NO_SHIFT;
- offset_mod.shiftbits = 0;
- offset_mod.mask = 0xFFFFFFFF;
-
r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
BEGIN_BATCH_NO_AUTOSTATE(3);
@@ -619,7 +601,7 @@ GLboolean r700SendPSState(context_t *context)
R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All,
pbo,
r700->ps.SQ_PGM_START_PS.u32All,
- RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod);
+ RADEON_GEM_DOMAIN_GTT, 0, 0);
END_BATCH();
BEGIN_BATCH_NO_AUTOSTATE(9);
@@ -637,15 +619,10 @@ GLboolean r700SendVSState(context_t *context)
{
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
struct radeon_bo * pbo;
- offset_modifiers offset_mod;
BATCH_LOCALS(&context->radeon);
pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
- offset_mod.shift = NO_SHIFT;
- offset_mod.shiftbits = 0;
- offset_mod.mask = 0xFFFFFFFF;
-
r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
BEGIN_BATCH_NO_AUTOSTATE(3);
@@ -653,7 +630,7 @@ GLboolean r700SendVSState(context_t *context)
R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All,
pbo,
r700->vs.SQ_PGM_START_VS.u32All,
- RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod);
+ RADEON_GEM_DOMAIN_GTT, 0, 0);
END_BATCH();
BEGIN_BATCH_NO_AUTOSTATE(6);
@@ -670,7 +647,6 @@ GLboolean r700SendFSState(context_t *context)
{
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
struct radeon_bo * pbo;
- offset_modifiers offset_mod;
BATCH_LOCALS(&context->radeon);
/* XXX fixme
@@ -684,10 +660,6 @@ GLboolean r700SendFSState(context_t *context)
r700->fs.SQ_PGM_CF_OFFSET_FS.u32All = 0;
/* XXX */
- offset_mod.shift = NO_SHIFT;
- offset_mod.shiftbits = 0;
- offset_mod.mask = 0xFFFFFFFF;
-
r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
BEGIN_BATCH_NO_AUTOSTATE(3);
@@ -695,7 +667,7 @@ GLboolean r700SendFSState(context_t *context)
R600_OUT_BATCH_RELOC(r700->fs.SQ_PGM_START_FS.u32All,
pbo,
r700->fs.SQ_PGM_START_FS.u32All,
- RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod);
+ RADEON_GEM_DOMAIN_GTT, 0, 0);
END_BATCH();
BEGIN_BATCH_NO_AUTOSTATE(6);
diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c
index bd4e0bf..5a1f04f 100644
--- a/src/mesa/drivers/dri/r600/r700_render.c
+++ b/src/mesa/drivers/dri/r600/r700_render.c
@@ -150,17 +150,12 @@ GLboolean r700SyncSurf(context_t *context,
{
BATCH_LOCALS(&context->radeon);
uint32_t cp_coher_size;
- offset_modifiers offset_mod;
if (pbo->size == 0xffffffff)
cp_coher_size = 0xffffffff;
else
cp_coher_size = ((pbo->size + 255) >> 8);
- offset_mod.shift = NO_SHIFT;
- offset_mod.shiftbits = 0;
- offset_mod.mask = 0xFFFFFFFF;
-
BEGIN_BATCH_NO_AUTOSTATE(5);
R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_SYNC, 3));
R600_OUT_BATCH(sync_type);
@@ -168,7 +163,7 @@ GLboolean r700SyncSurf(context_t *context,
R600_OUT_BATCH_RELOC(0,
pbo,
0,
- read_domain, write_domain, 0, &offset_mod); // ???
+ read_domain, write_domain, 0); // ???
R600_OUT_BATCH(10);
END_BATCH();
diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c
index 8652f1d..1c5c20f 100644
--- a/src/mesa/drivers/dri/r600/r700_vertprog.c
+++ b/src/mesa/drivers/dri/r600/r700_vertprog.c
@@ -340,8 +340,6 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx)
struct r700_vertex_program *vp
= (struct r700_vertex_program *)ctx->VertexProgram._Current;
- struct gl_program_parameter_list *paramList;
-
if(GL_FALSE == vp->loaded)
{
if(vp->r700Shader.bNeedsAssembly == GL_TRUE)
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