Mesa (master): i965: Fix tiling for FBO depth attachments by making DEPTH_COMPONENT Y tiled.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: bd10f0e84f1491363d76d92dcbd410ab5cc43dbe
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd10f0e84f1491363d76d92dcbd410ab5cc43dbe

Author: Eric Anholt <eric at anholt.net>
Date:   Fri Jun 12 08:44:40 2009 -0700

i965: Fix tiling for FBO depth attachments by making DEPTH_COMPONENT Y tiled.

This may hurt if miptree relayout occurs, since we can't blit Y tiled
objects.  But it corrects depth tests on FBOs using textures.

---

 src/mesa/drivers/dri/intel/intel_mipmap_tree.c |   10 +++++++---
 src/mesa/drivers/dri/intel/intel_regions.c     |    2 +-
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 0d34f28..fcfed9e 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -113,9 +113,13 @@ intel_miptree_create(struct intel_context *intel,
    uint32_t tiling;
 
    if (intel->use_texture_tiling && compress_byte == 0 &&
-       intel->intelScreen->kernel_exec_fencing)
-      tiling = I915_TILING_X;
-   else
+       intel->intelScreen->kernel_exec_fencing) {
+      if (IS_965(intel->intelScreen->deviceID) &&
+	  internal_format == GL_DEPTH_COMPONENT)
+	 tiling = I915_TILING_Y;
+      else
+	 tiling = I915_TILING_X;
+   } else
       tiling = I915_TILING_NONE;
 
    mt = intel_miptree_create_internal(intel, target, internal_format,
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index 49bcb3c..7c3b483 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -189,7 +189,7 @@ intel_region_alloc(struct intel_context *intel,
 					pitch, buffer);
 
    if (tiling != I915_TILING_NONE) {
-      assert(((pitch * cpp) & 511) == 0);
+      assert(((pitch * cpp) & 127) == 0);
       drm_intel_bo_set_tiling(buffer, &tiling, pitch * cpp);
       drm_intel_bo_get_tiling(buffer, &region->tiling, &region->bit_6_swizzle);
    }