Mesa (master): i965: Fix DP write channel ordering on Sandybridge.
Eric Anholt
anholt at kemper.freedesktop.org
Fri Aug 20 23:18:22 UTC 2010
Module: Mesa
Branch: master
Commit: b7004350fac622ce4b45a31773ac7b0c186e66d6
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b7004350fac622ce4b45a31773ac7b0c186e66d6
Author: Eric Anholt <eric at anholt.net>
Date: Thu Jul 8 13:16:40 2010 -0700
i965: Fix DP write channel ordering on Sandybridge.
The SIMD16 message no longer has the goofy interleaved format that
made Compr4 compression necessary before.
---
src/mesa/drivers/dri/i965/brw_wm_emit.c | 27 +++++++++++++++++++++++++--
1 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c
index f01fffb..f2ace7d 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -1294,6 +1294,7 @@ void emit_fb_write(struct brw_wm_compile *c,
{
struct brw_compile *p = &c->func;
struct brw_context *brw = p->brw;
+ struct intel_context *intel = &brw->intel;
GLuint nr = 2;
GLuint channel;
@@ -1308,8 +1309,30 @@ void emit_fb_write(struct brw_wm_compile *c,
brw_push_insn_state(p);
for (channel = 0; channel < 4; channel++) {
- if (c->dispatch_width == 16 && brw->has_compr4) {
- /* By setting the high bit of the MRF register number, we indicate
+ if (intel->gen >= 6) {
+ /* gen6 SIMD16 single source DP write looks like:
+ * m + 0: r0
+ * m + 1: r1
+ * m + 2: g0
+ * m + 3: g1
+ * m + 4: b0
+ * m + 5: b1
+ * m + 6: a0
+ * m + 7: a1
+ */
+ brw_MOV(p, brw_message_reg(nr + channel * 2), arg0[channel]);
+ } else if (c->dispatch_width == 16 && brw->has_compr4) {
+ /* pre-gen6 SIMD16 single source DP write looks like:
+ * m + 0: r0
+ * m + 1: g0
+ * m + 2: b0
+ * m + 3: a0
+ * m + 4: r1
+ * m + 5: g1
+ * m + 6: b1
+ * m + 7: a1
+ *
+ * By setting the high bit of the MRF register number, we indicate
* that we want COMPR4 mode - instead of doing the usual destination
* + 1 for the second half we get destination + 4.
*/
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