Mesa (master): i965: Use intel->gen >= 6 instead of IS_GEN6.

Eric Anholt anholt at kemper.freedesktop.org
Sun Aug 22 07:53:39 UTC 2010


Module: Mesa
Branch: master
Commit: 527a9a4de218cae89d7faf92788f88ce1f9387b6
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=527a9a4de218cae89d7faf92788f88ce1f9387b6

Author: Eric Anholt <eric at anholt.net>
Date:   Sat Aug 21 23:47:06 2010 -0700

i965: Use intel->gen >= 6 instead of IS_GEN6.

---

 src/mesa/drivers/dri/i965/brw_draw_upload.c  |    4 ++--
 src/mesa/drivers/dri/i965/brw_misc_state.c   |    2 +-
 src/mesa/drivers/dri/i965/brw_state_upload.c |    4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index f07aab8..249e874 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -476,7 +476,7 @@ static void brw_emit_vertices(struct brw_context *brw)
    if (brw->vb.nr_enabled == 0) {
       BEGIN_BATCH(3);
       OUT_BATCH((CMD_VERTEX_ELEMENT << 16) | 1);
-      if (IS_GEN6(intel->intelScreen->deviceID)) {
+      if (intel->gen >= 6) {
 	 OUT_BATCH((0 << GEN6_VE0_INDEX_SHIFT) |
 		   GEN6_VE0_VALID |
 		   (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
@@ -553,7 +553,7 @@ static void brw_emit_vertices(struct brw_context *brw)
 	 break;
       }
 
-      if (IS_GEN6(intel->intelScreen->deviceID)) {
+      if (intel->gen >= 6) {
 	 OUT_BATCH((i << GEN6_VE0_INDEX_SHIFT) |
 		   GEN6_VE0_VALID |
 		   (format << BRW_VE0_FORMAT_SHIFT) |
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 572175f..565a9e3 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -281,7 +281,7 @@ static void emit_depthbuffer(struct brw_context *brw)
       }
 
       assert(region->tiling != I915_TILING_X);
-      if (IS_GEN6(intel->intelScreen->deviceID))
+      if (intel->gen >= 6)
 	 assert(region->tiling != I915_TILING_NONE);
 
       BEGIN_BATCH(len);
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index f92a19c..9726612 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -351,7 +351,7 @@ void brw_validate_state( struct brw_context *brw )
 
    brw_add_validated_bo(brw, intel->batch->buf);
 
-   if (IS_GEN6(intel->intelScreen->deviceID)) {
+   if (intel->gen >= 6) {
       atoms = gen6_atoms;
       num_atoms = ARRAY_SIZE(gen6_atoms);
    } else {
@@ -425,7 +425,7 @@ void brw_upload_state(struct brw_context *brw)
    const struct brw_tracked_state **atoms;
    int num_atoms;
 
-   if (IS_GEN6(intel->intelScreen->deviceID)) {
+   if (intel->gen >= 6) {
       atoms = gen6_atoms;
       num_atoms = ARRAY_SIZE(gen6_atoms);
    } else {




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