Mesa (master): i915g: implement unfenced relocs for textures using tiling bits

[Jakob Bornecrantz]

Module: Mesa
Branch: master
Commit: f34fd58ec92b9344982b4a5a4b9e05fe4b151a64
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f34fd58ec92b9344982b4a5a4b9e05fe4b151a64

Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date:   Wed Dec  1 21:03:13 2010 +0100

i915g: implement unfenced relocs for textures using tiling bits

Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Jakob Bornecrantz <wallbraker at gmail.com>
Signed-off-by: Jakob Bornecrantz <wallbraker at gmail.com>

---

 src/gallium/drivers/i915/i915_reg.h           |    2 +-
 src/gallium/drivers/i915/i915_state_emit.c    |    3 +--
 src/gallium/drivers/i915/i915_state_sampler.c |   20 ++++++++++++++++++--
 3 files changed, 20 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/i915/i915_reg.h b/src/gallium/drivers/i915/i915_reg.h
index cc28891..1f6d8ac 100644
--- a/src/gallium/drivers/i915/i915_reg.h
+++ b/src/gallium/drivers/i915/i915_reg.h
@@ -753,7 +753,7 @@
 #define    MT_COMPRESS_DXT1_RGB		   (4<<3)
 #define MS3_USE_FENCE_REGS              (1<<2)
 #define MS3_TILED_SURFACE             (1<<1)
-#define MS3_TILE_WALK                 (1<<0)
+#define MS3_TILE_WALK_Y                (1<<0)
 
 #define MS4_PITCH_SHIFT                 21
 #define MS4_CUBE_FACE_ENA_NEGX          (1<<20)
diff --git a/src/gallium/drivers/i915/i915_state_emit.c b/src/gallium/drivers/i915/i915_state_emit.c
index 803cc90..8d912ca 100644
--- a/src/gallium/drivers/i915/i915_state_emit.c
+++ b/src/gallium/drivers/i915/i915_state_emit.c
@@ -308,12 +308,11 @@ i915_emit_hardware_state(struct i915_context *i915 )
                if (enabled & (1 << unit)) {
                   struct i915_texture *texture = i915_texture(i915->fragment_sampler_views[unit]->texture);
                   struct i915_winsys_buffer *buf = texture->buffer;
-                  uint offset = 0;
                   assert(buf);
 
                   count++;
 
-                  OUT_RELOC_FENCED(buf, I915_USAGE_SAMPLER, offset);
+                  OUT_RELOC(buf, I915_USAGE_SAMPLER, 0);
                   OUT_BATCH(i915->current.texbuffer[unit][0]); /* MS3 */
                   OUT_BATCH(i915->current.texbuffer[unit][1]); /* MS4 */
                }
diff --git a/src/gallium/drivers/i915/i915_state_sampler.c b/src/gallium/drivers/i915/i915_state_sampler.c
index 9771274..916cb76 100644
--- a/src/gallium/drivers/i915/i915_state_sampler.c
+++ b/src/gallium/drivers/i915/i915_state_sampler.c
@@ -243,6 +243,23 @@ static uint translate_texture_format(enum pipe_format pipeFormat)
    }
 }
 
+static inline uint32_t
+ms3_tiling_bits(enum i915_winsys_buffer_tile tiling)
+{
+         uint32_t tiling_bits = 0;
+
+         switch (tiling) {
+         case I915_TILE_Y:
+            tiling_bits |= MS3_TILE_WALK_Y;
+         case I915_TILE_X:
+            tiling_bits |= MS3_TILED_SURFACE;
+         case I915_TILE_NONE:
+            break;
+         }
+
+         return tiling_bits;
+}
+
 static void update_map(struct i915_context *i915,
                        uint unit,
                        const struct i915_texture *tex,
@@ -254,7 +271,6 @@ static void update_map(struct i915_context *i915,
    const uint width = pt->width0, height = pt->height0, depth = pt->depth0;
    const uint num_levels = pt->last_level;
    unsigned max_lod = num_levels * 4;
-   unsigned tiled = MS3_USE_FENCE_REGS;
 
    assert(tex);
    assert(width);
@@ -272,7 +288,7 @@ static void update_map(struct i915_context *i915,
       (((height - 1) << MS3_HEIGHT_SHIFT)
        | ((width - 1) << MS3_WIDTH_SHIFT)
        | format
-       | tiled);
+       | ms3_tiling_bits(tex->tiling));
 
    /*
     * XXX When min_filter != mag_filter and there's just one mipmap level,