Mesa (gallium-array-textures): 39 new commits
Roland Scheidegger
sroland at kemper.freedesktop.org
Thu Dec 2 03:34:43 UTC 2010
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a45bd509014743d21a532194d7b658a1aeb00cb7
Merge: 1aeca287a827f29206078fa1204715a477072c08 32e1e591467d9a28c2ac4d2e17af7be2dc429d43
Author: Roland Scheidegger <sroland at vmware.com>
Date: Thu Dec 2 04:32:06 2010 +0100
Merge remote branch 'origin/master' into gallium-array-textures
Conflicts:
src/gallium/drivers/i915/i915_resource_texture.c
src/gallium/drivers/i915/i915_state_emit.c
src/gallium/drivers/i915/i915_surface.c
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=32e1e591467d9a28c2ac4d2e17af7be2dc429d43
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Wed Dec 1 16:59:36 2010 +0800
i965: add support for polygon mode on Sandybridge.
This fixes some mesa demos such as fslight/engine in wireframe mode.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=de3ff5af49369d187d88e5399f388c6e48c5384f
Author: Jakob Bornecrantz <wallbraker at gmail.com>
Date: Mon Nov 29 20:53:26 2010 +0100
i915g: Make sure that new vbo gets updated
Malloc likes to reuse old address as soon as possible this would cause the
new vbo buffer to get the same address as the old. So make sure we set it to
NULL when we allocate a new one. This fixes ipers which will fill up a couple
of VBO buffers per frame.
Signed-off-by: Jakob Bornecrantz <wallbraker at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=442e567aa0f0cf91cbd30ffdfc74d281d619dd5e
Author: Jakob Bornecrantz <wallbraker at gmail.com>
Date: Mon Nov 29 00:14:59 2010 +0100
i915g: Improve debug printing for textures
Signed-off-by: Jakob Bornecrantz <wallbraker at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f6476822a0b1a85a8b60363b0d3bb85f0b54c395
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Wed Dec 1 21:57:41 2010 +0100
i915g: Fix closure of full batch buffers
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
[danvet: incorporate comments by Dr_Jakob]
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Jakob Bornecrantz <wallbraker at gmail.com>
Signed-off-by: Jakob Bornecrantz <wallbraker at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=600454084b3180214993b54a181be49d28ca5091
Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date: Sun Nov 21 17:56:09 2010 +0100
i915g: track TODO items
Just as a reminder for all things currently broken with i915g.
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Jakob Bornecrantz <wallbraker at gmail.com>
Signed-off-by: Jakob Bornecrantz <wallbraker at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0246b2bf2799e20ca390777201e5023b897e2b94
Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date: Sun Nov 28 21:56:24 2010 +0100
i915g: assert(depth_surface->offset == 0)
Shouldn't happen and not supported, anyway.
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Jakob Bornecrantz <wallbraker at gmail.com>
Signed-off-by: Jakob Bornecrantz <wallbraker at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a47a25d2cc7789b95e88c1d46b29f98fd728004
Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date: Sun Nov 28 21:37:03 2010 +0100
i915g: enable x-tiling for render targets
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Jakob Bornecrantz <wallbraker at gmail.com>
Signed-off-by: Jakob Bornecrantz <wallbraker at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8af684e37e7bacfc40aa9cd5f30ca1f692d0c62c
Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date: Wed Dec 1 21:04:56 2010 +0100
i915g: switch rendering to mipmapped textures to (x,y) offsets
Byte offsets simply don't work with tiled render targets when using
tiling bits. Luckily we can cox the hw into doing the right thing
with the DRAWING_RECT command by disabling the drawing rect offset
for the depth buffer.
Minor fixes by Jakob Bornecrantz.
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Jakob Bornecrantz <wallbraker at gmail.com>
Signed-off-by: Jakob Bornecrantz <wallbraker at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9493fe85d1b10efc06e8c34de31971dc6e6a6062
Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date: Sat Nov 20 11:17:55 2010 +0100
i915g: enable X-tiling for textures
Tiling is rather fragile in general and results in pure blackness when
unlucky. Hence add a new option to disable tiling.
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Jakob Bornecrantz <wallbraker at gmail.com>
Signed-off-by: Jakob Bornecrantz <wallbraker at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=32345610cc2b1936c1df43b1526d56046b2b5168
Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date: Sat Nov 20 10:23:03 2010 +0100
i915g: don't pot-align stride for tiled buffers
libdrm will do this for us, if it's required (i.e. if tiling is
possible).
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Jakob Bornecrantz <wallbraker at gmail.com>
Signed-off-by: Jakob Bornecrantz <wallbraker at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6ae6e0c6feacd89a7e3db4db5c4ea800cbe40397
Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date: Sat Nov 20 10:00:38 2010 +0100
i915g: postpone mipmap/face offset calculation
libdrm-intel can refuse to tile buffers for various reasons. For
potentially tiled buffers the stride is therefore only known after
the iws->buffer_create_tiled call. Unconditionally rounding up to whatever
tiling requires wastes space, so rework the code to not use tex->stride
in the layout code.
Luckily only the mimap/face offset calculation uses it which can easily
be solved by storing an (x, y) coordinate pair. Furthermore this will
be usefull later for properly supporting rendering into the different
levels of tiled mipmap textures.
v2: switch to nblocks(x|y): More in line with gallium and better
suited for rendering into mipmap textures.
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Jakob Bornecrantz <wallbraker at gmail.com>
Signed-off-by: Jakob Bornecrantz <wallbraker at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f34fd58ec92b9344982b4a5a4b9e05fe4b151a64
Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date: Wed Dec 1 21:03:13 2010 +0100
i915g: implement unfenced relocs for textures using tiling bits
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Jakob Bornecrantz <wallbraker at gmail.com>
Signed-off-by: Jakob Bornecrantz <wallbraker at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a95e694eaf3b40c86fbe8116fc3b5f1add365898
Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date: Wed Dec 1 20:59:45 2010 +0100
i915g: implement unfenced color&depth buffer using tiling bits
v2: Clarify tiling bit calculation as suggested by Chris Wilson.
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Jakob Bornecrantz <wallbraker at gmail.com>
Signed-off-by: Jakob Bornecrantz <wallbraker at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2ff0879a6365e7f7d7e5277274bc965ad57a82b4
Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date: Sun Nov 21 20:25:33 2010 +0100
i915g: return tiling in iws->buffer_from_handle
This is needed to properly implement tiling flags. And the gem
implemention fo buffer_from_handle already calls get_tiling, so
it's for free.
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Jakob Bornecrantz <wallbraker at gmail.com>
Signed-off-by: Jakob Bornecrantz <wallbraker at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=135b083461f8a5a220d86f57af018f6f0316d2bb
Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date: Sun Nov 21 20:21:00 2010 +0100
i915g: prepare winsys/batchbuffer for execbuf2
Wire up a fenced parameter, switch all relocations to _FENCED
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Jakob Bornecrantz <wallbraker at gmail.com>
Signed-off-by: Jakob Bornecrantz <wallbraker at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c608403383f3c31e19b70c578ac66443f259967
Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date: Sun Nov 21 20:36:01 2010 +0100
i915g: switch to tiled allocations, kill set_fence
This way relaxed fencing is handled by libdrm. And buffers _can't_
ever change their tiling.
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Jakob Bornecrantz <wallbraker at gmail.com>
Signed-off-by: Jakob Bornecrantz <wallbraker at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4a666488c4e3067eed984e272149411cc2198c77
Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date: Sun Nov 21 20:34:44 2010 +0100
i915g: add winsys function to create tiled buffers
Different kernels have different restrictions for tiled buffers.
Hence use the libdrm abstraction to calculate the necessary
stride and height alignment requirements.
Not yet used.
v2: Incorporate review comments from Jakob Bornecrantz
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Jakob Bornecrantz <wallbraker at gmail.com>
Signed-off-by: Jakob Bornecrantz <wallbraker at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c62f5c7e7bc3ed84677805b3800fbcfa93c419ea
Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date: Sun Nov 21 19:06:48 2010 +0100
i915g: drop alignment parameter from iws->buffer_create
It's unnecessary. The kernel gem ignores it totally and we can't
run on the old userspace fake bo manager due to lack of dri2.
Also drop the redundant name string from the sw winsys as suggested
by Jakob Bornecrantz
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Jakob Bornecrantz <wallbraker at gmail.com>
Signed-off-by: Jakob Bornecrantz <wallbraker at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b4f585665c31b1f80d909e38b3b2a9fab0c03076
Author: Eric Anholt <eric at anholt.net>
Date: Wed Dec 1 15:55:53 2010 -0800
glsl: Mark the array access for whole-array comparisons.
By not doing so, the uniform contents of
glsl-uniform-non-uniform-array-compare.shader_test was getting thrown
out since nobody was recorded as dereferencing the array.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f361f8a8a9a71d84fc569445902adacc2f2cc069
Author: Eric Anholt <eric at anholt.net>
Date: Wed Dec 1 15:37:10 2010 -0800
i965: Add support for loops in the VS.
This follows the changes done for the FS alongside the EU emit code.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=251d15d888dfaea045447f9e56ea094cb726830b
Author: Eric Anholt <eric at anholt.net>
Date: Wed Dec 1 15:36:26 2010 -0800
i965: Enable IF statements in the VS.
While the actual IF instructions were fixed by Zhenyu, we were still
flattening them to conditional moves.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=843a6a308e05bd4bf2056e08ec65ac4770097b93
Author: Eric Anholt <eric at anholt.net>
Date: Wed Dec 1 14:02:14 2010 -0800
i965: Add support for gen6 CONTINUE instruction emit.
At this point, piglit tests for fragment shader loops are working.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=00e5a743e2ee3981a34b95067a97fa73c0f5d779
Author: Eric Anholt <eric at anholt.net>
Date: Wed Dec 1 11:46:46 2010 -0800
i965: Add support for gen6 BREAK ISA emit.
There are now two targets: the hop-to-end-of-block target, and the
target for where to resume execution for active channels.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4890e0f09c934e3ffb692b417e5444e43685c876
Author: Eric Anholt <eric at anholt.net>
Date: Wed Dec 1 10:45:52 2010 -0800
i965: Add support for gen6 DO/WHILE ISA emit.
There's no more DO since there's no more mask stack, and WHILE has
been shuffled like IF was.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a9f62881a316539658845a98b856f1bf31ca44bc
Author: Eric Anholt <eric at anholt.net>
Date: Wed Dec 1 15:00:08 2010 -0800
i965: Dump the WHILE jump distance on gen6.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fcf6b353bfd860aa7bcc708858bef313c6fd7031
Author: Marek Olšák <maraeo at gmail.com>
Date: Wed Dec 1 22:49:02 2010 +0100
r300g: disable ARB_texture_swizzle if S3TC is enabled on r3xx-only
r3xx cannot swizzle compressed textures. r4xx+ is unaffected.
NOTE: This is a candidate for the 7.9 branch.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6478a4de14d368bf85ba3477d73fd1bd91067e86
Author: Marek Olšák <maraeo at gmail.com>
Date: Tue Nov 30 23:28:43 2010 +0100
r300g: fix texture swizzling with compressed textures on r400-r500
This fixes all S3TC piglit/texwrap tests.
NOTE: This is a candidate for the 7.9 branch.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c92550be64abd454560556599cd95b237f4375b1
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Dec 1 11:57:33 2010 -0800
i915: Correctly generate unconditional KIL instructions
Fixes piglit test glsl-fs-discard-03.
NOTE: This is a candidate for the 7.9 branch.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b6dbc06742af4cbd86869243640c35aa7025766c
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Nov 24 22:21:34 2010 -0800
i915: Request that POW instructions be lowered
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c4285be9a5bd1adaa89050989374b95a9a601cdc
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Nov 24 22:21:10 2010 -0800
glsl: Lower ir_binop_pow to a sequence of EXP2 and LOG2
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=da61afa7388f1ce50ef612b89aba2302a052a3bb
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Nov 24 14:03:57 2010 -0800
glsl: Use M_LOG2E constant instead of calling log2
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d2d7a273c51127677d394d1bb9484a2d85c5dcd2
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 29 11:00:10 2010 -0800
glsl: Add comments to lower_jumps (from the commit message).
This is essentially Luca's commit message, but placed at the top of the
file.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1802cb9bafc4125300870be51e8b22ddd795d61e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 29 10:59:16 2010 -0800
glsl: Remove "discard" support from lower_jumps.
The new lower_discard and opt_discard_simplification passes should
handle all the necessary transformations, so lower_jumps doesn't need to
support it.
Also, lower_jumps incorrectly handled conditional discards - it would
unconditionally truncate all code after the discard. Rather than fixing
the bug, simply remove the code.
NOTE: This is a candidate for the 7.9 branch.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=940df10100d740ef27fa39026fd51c3199ed3d62
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 25 01:09:26 2010 -0800
glsl: Add a lowering pass to move discards out of if-statements.
This should allow lower_if_to_cond_assign to work in the presence of
discards, fixing bug #31690 and likely #31983.
NOTE: This is a candidate for the 7.9 branch.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a1d063c6d679c2155f5eb80f1cb94368d36bf2c
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Nov 24 22:02:26 2010 -0800
glsl: Add an optimization pass to simplify discards.
NOTE: This is a candidate for the 7.9 branch.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ead2ea89f42b40edc56ddf8c6ce1df4efdcefe2a
Author: Marek Olšák <maraeo at gmail.com>
Date: Thu Nov 25 03:13:36 2010 -0800
ir_to_mesa: Add support for conditional discards.
NOTE: This is a candidate for the 7.9 branch.
Signed-off-by: Marek Olšák <maraeo at gmail.com>
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2ca9256911d8d5aed0de2b3d53d8ef998b105176
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Wed Dec 1 13:22:00 2010 -0500
r600c: fix some opcodes on evergreen
There were a few places where we were using the wrong opcodes
on evergreen. arl still needs to be fixed on evergreen; see
r600g for reference.
NOTE: This is a candidate for the 7.9 branch.
Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e6d798948e00e255b80a69562a7d262257f77ee5
Author: Marek Olšák <maraeo at gmail.com>
Date: Wed Dec 1 16:44:22 2010 +0100
r300/compiler: implement and lower OPCODE_CLAMP
Needed for st/vega.
More information about the mesa-commit
mailing list