Mesa (master): i965: Align gen6 push constant size to dispatch width.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 3f8bcb0d998820594ea288e4607462fa4479859f
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f8bcb0d998820594ea288e4607462fa4479859f

Author: Eric Anholt <eric at anholt.net>
Date:   Fri Dec  3 16:50:19 2010 -0800

i965: Align gen6 push constant size to dispatch width.

The FS backend is fine with register level granularity.  But for the
brw_wm_emit.c backend, it expects pairs of regs to be used for the
constants, because the whole world is pairs of regs.  If an odd number
got used, we went looking for interpolation in the wrong place.

---

 src/mesa/drivers/dri/i965/gen6_wm_state.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index 0d839de..8968cae 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -105,7 +105,8 @@ upload_wm_state(struct brw_context *brw)
 		(5 - 2));
       OUT_RELOC(brw->wm.push_const_bo,
 		I915_GEM_DOMAIN_RENDER, 0, /* XXX: bad domain */
-		ALIGN(brw->wm.prog_data->nr_params, 8) / 8 - 1);
+		ALIGN(brw->wm.prog_data->nr_params,
+		      brw->wm.prog_data->dispatch_width) / 8 - 1);
       OUT_BATCH(0);
       OUT_BATCH(0);
       OUT_BATCH(0);