Mesa (7.9): i965: Correct the dp_read message descriptor setup on g4x.

[Eric Anholt]

Module: Mesa
Branch: 7.9
Commit: ecb68d51aadfa8cb5f8dbba59ecc402f0e20da10
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ecb68d51aadfa8cb5f8dbba59ecc402f0e20da10

Author: Eric Anholt <eric at anholt.net>
Date:   Thu Dec 23 14:27:11 2010 -0800

i965: Correct the dp_read message descriptor setup on g4x.

It's mostly like gen4 message descriptor setup, except that the sizes
of type/control changed to be like gen5.  Fixes 21 piglit cases on
gm45, including the regressions in bug #32311 from increased VS
constant buffer usage.
(cherry picked from commit 5dc53444c8323c1787dddbe6b67048828df9c684)

---

 src/mesa/drivers/dri/i965/brw_disasm.c  |    2 +-
 src/mesa/drivers/dri/i965/brw_eu_emit.c |   10 ++++++++++
 src/mesa/drivers/dri/i965/brw_structs.h |   12 ++++++++++++
 3 files changed, 23 insertions(+), 1 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c
index 9052082..7b6ff33 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -961,7 +961,7 @@ int brw_disasm (FILE *file, struct brw_instruction *inst, int gen)
 			inst->bits3.dp_render_cache.send_commit_msg,
 			inst->bits3.dp_render_cache.msg_length,
 			inst->bits3.dp_render_cache.response_length);
-	    } else if (gen >= 5) {
+	    } else if (gen >= 5 /* FINISHME: || is_g4x */) {
 		format (file, " (%d, %d, %d)",
 			inst->bits3.dp_read_gen5.binding_table_index,
 			inst->bits3.dp_read_gen5.msg_control,
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 09cc8b2..33d55d1 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -520,6 +520,16 @@ static void brw_set_dp_read_message( struct brw_context *brw,
        insn->bits3.dp_read_gen5.end_of_thread = end_of_thread;
        insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_DATAPORT_READ;
        insn->bits2.send_gen5.end_of_thread = end_of_thread;
+   } else if (intel->is_g4x) {
+       insn->bits3.dp_read_g4x.binding_table_index = binding_table_index; /*0:7*/
+       insn->bits3.dp_read_g4x.msg_control = msg_control;  /*8:10*/
+       insn->bits3.dp_read_g4x.msg_type = msg_type;  /*11:13*/
+       insn->bits3.dp_read_g4x.target_cache = target_cache;  /*14:15*/
+       insn->bits3.dp_read_g4x.response_length = response_length;  /*16:19*/
+       insn->bits3.dp_read_g4x.msg_length = msg_length;  /*20:23*/
+       insn->bits3.dp_read_g4x.msg_target = BRW_MESSAGE_TARGET_DATAPORT_READ; /*24:27*/
+       insn->bits3.dp_read_g4x.pad1 = 0;
+       insn->bits3.dp_read_g4x.end_of_thread = end_of_thread;
    } else {
        insn->bits3.dp_read.binding_table_index = binding_table_index; /*0:7*/
        insn->bits3.dp_read.msg_control = msg_control;  /*8:11*/
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index 7b91987..61eb587 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -1624,6 +1624,18 @@ struct brw_instruction
 
       struct {
 	 GLuint binding_table_index:8;
+	 GLuint msg_control:3;
+	 GLuint msg_type:3;
+	 GLuint target_cache:2;
+	 GLuint response_length:4;
+	 GLuint msg_length:4;
+	 GLuint msg_target:4;
+	 GLuint pad1:3;
+	 GLuint end_of_thread:1;
+      } dp_read_g4x;
+
+      struct {
+	 GLuint binding_table_index:8;
 	 GLuint msg_control:3;  
 	 GLuint msg_type:3;  
 	 GLuint target_cache:2;