Mesa (master): intel: Use drm_intel_bo_alloc_tiled for region allocs.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 179d2c0e0bcf96fc40107882ccab909af8c89853
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=179d2c0e0bcf96fc40107882ccab909af8c89853

Author: Eric Anholt <eric at anholt.net>
Date:   Tue Mar  2 15:34:17 2010 -0800

intel: Use drm_intel_bo_alloc_tiled for region allocs.

This moves the logic for how to align pitches, heights, and sizes of
objects to one central location.  Fixes rendering with texture tiling
on i915.  Note that current libdrm is required for the change for
I915_TILING_NONE pitch alignment.

---

 configure.ac                               |    2 +-
 src/mesa/drivers/dri/intel/intel_regions.c |   39 ++++++++--------------------
 2 files changed, 12 insertions(+), 29 deletions(-)

diff --git a/configure.ac b/configure.ac
index d108ecd..e807d4a 100644
--- a/configure.ac
+++ b/configure.ac
@@ -804,7 +804,7 @@ AC_SUBST([DRI_LIB_DEPS])
 
 case $DRI_DIRS in
 *i915*|*i965*)
-    PKG_CHECK_MODULES([INTEL], [libdrm_intel])
+    PKG_CHECK_MODULES([INTEL], [libdrm_intel >= 2.4.19])
     ;;
 esac
 
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index f63d3a4..e3c0635 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -180,36 +180,19 @@ intel_region_alloc(struct intel_context *intel,
 {
    dri_bo *buffer;
    struct intel_region *region;
+   unsigned long flags = 0;
+   unsigned long aligned_pitch;
 
-   /* If we're tiled, our allocations are in 8 or 32-row blocks, so
-    * failure to align our height means that we won't allocate enough pages.
-    *
-    * If we're untiled, we still have to align to 2 rows high because the
-    * data port accesses 2x2 blocks even if the bottom row isn't to be
-    * rendered, so failure to align means we could walk off the end of the
-    * GTT and fault.
-    */
-   if (tiling == I915_TILING_X)
-      height = ALIGN(height, 8);
-   else if (tiling == I915_TILING_Y)
-      height = ALIGN(height, 32);
-   else
-      height = ALIGN(height, 2);
-
-   /* If we're untiled, we have to align to 2 rows high because the
-    * data port accesses 2x2 blocks even if the bottom row isn't to be
-    * rendered, so failure to align means we could walk off the end of the
-    * GTT and fault.
+   if (expect_accelerated_upload)
+      flags |= BO_ALLOC_FOR_RENDER;
+
+   buffer = drm_intel_bo_alloc_tiled(intel->bufmgr, "region",
+				     width, height, cpp,
+				     &tiling, &aligned_pitch, flags);
+   /* We've already chosen a pitch as part of miptree layout.  It had
+    * better be the same.
     */
-   height = ALIGN(height, 2);
-
-   if (expect_accelerated_upload) {
-      buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region",
-					     pitch * cpp * height, 64);
-   } else {
-      buffer = drm_intel_bo_alloc(intel->bufmgr, "region",
-				  pitch * cpp * height, 64);
-   }
+   assert(aligned_pitch == pitch * cpp);
 
    region = intel_region_alloc_internal(intel, cpp, width, height,
 					pitch, buffer);