Mesa (master): i965: Use SENDC on the first render target write on gen6.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 1732a8bc72fe0a8eaf7449eda65eba1a017ae909
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1732a8bc72fe0a8eaf7449eda65eba1a017ae909

Author: Eric Anholt <eric at anholt.net>
Date:   Tue Oct 26 09:35:34 2010 -0700

i965: Use SENDC on the first render target write on gen6.

This is apparently required, as the thread will be initiated while it
still has dependencies, and this is what waits for those to be
resolved before writing color.

---

 src/mesa/drivers/dri/i965/brw_defines.h |    1 +
 src/mesa/drivers/dri/i965/brw_disasm.c  |   10 +++++++---
 src/mesa/drivers/dri/i965/brw_eu_emit.c |    6 +++++-
 3 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 9633c95..6c3db61 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -551,6 +551,7 @@
 #define BRW_OPCODE_POP        47
 #define BRW_OPCODE_WAIT       48
 #define BRW_OPCODE_SEND       49
+#define BRW_OPCODE_SENDC      50
 #define BRW_OPCODE_MATH       56
 #define BRW_OPCODE_ADD        64
 #define BRW_OPCODE_MUL        65
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c
index 12b8f2e..5797262 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -72,6 +72,7 @@ struct {
     [BRW_OPCODE_CMPN] = { .name = "cmpn", .nsrc = 2, .ndst = 1 },
 
     [BRW_OPCODE_SEND] = { .name = "send", .nsrc = 1, .ndst = 1 },
+    [BRW_OPCODE_SENDC] = { .name = "sendc", .nsrc = 1, .ndst = 1 },
     [BRW_OPCODE_NOP] = { .name = "nop", .nsrc = 0, .ndst = 0 },
     [BRW_OPCODE_JMPI] = { .name = "jmpi", .nsrc = 1, .ndst = 0 },
     [BRW_OPCODE_IF] = { .name = "if", .nsrc = 2, .ndst = 0 },
@@ -876,7 +877,8 @@ int brw_disasm (FILE *file, struct brw_instruction *inst, int gen)
 	string (file, " ");
 	err |= control (file, "function", math_function,
 			inst->header.destreg__conditionalmod, NULL);
-    } else if (inst->header.opcode != BRW_OPCODE_SEND)
+    } else if (inst->header.opcode != BRW_OPCODE_SEND &&
+	       inst->header.opcode != BRW_OPCODE_SENDC)
 	err |= control (file, "conditional modifier", conditional_modifier,
 			inst->header.destreg__conditionalmod, NULL);
 
@@ -907,7 +909,8 @@ int brw_disasm (FILE *file, struct brw_instruction *inst, int gen)
 	err |= src1 (file, inst);
     }
 
-    if (inst->header.opcode == BRW_OPCODE_SEND) {
+    if (inst->header.opcode == BRW_OPCODE_SEND ||
+	inst->header.opcode == BRW_OPCODE_SENDC) {
 	int target;
 
 	if (gen >= 6)
@@ -1070,7 +1073,8 @@ int brw_disasm (FILE *file, struct brw_instruction *inst, int gen)
 	err |= control (file, "thread control", thread_ctrl, inst->header.thread_control, &space);
 	if (gen >= 6)
 	    err |= control (file, "acc write control", accwr, inst->header.acc_wr_control, &space);
-	if (inst->header.opcode == BRW_OPCODE_SEND)
+	if (inst->header.opcode == BRW_OPCODE_SEND ||
+	    inst->header.opcode == BRW_OPCODE_SENDC)
 	    err |= control (file, "end of thread", end_of_thread,
 			    inst->bits3.generic.end_of_thread, &space);
 	if (space)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index d5f24c2..3744e81 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -1735,7 +1735,11 @@ void brw_fb_WRITE(struct brw_compile *p,
    GLuint msg_control, msg_type;
    GLboolean header_present = GL_TRUE;
 
-   insn = next_insn(p, BRW_OPCODE_SEND);
+   if (intel->gen >= 6 && binding_table_index == 0) {
+      insn = next_insn(p, BRW_OPCODE_SENDC);
+   } else {
+      insn = next_insn(p, BRW_OPCODE_SEND);
+   }
    /* The execution mask is ignored for render target writes. */
    insn->header.predicate_control = 0;
    insn->header.compression_control = BRW_COMPRESSION_NONE;