Mesa (master): i965: Disable register spilling on gen6 until it's fixed.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: bb4f12f53875707a0d3c1eb254745b6250c42951
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=bb4f12f53875707a0d3c1eb254745b6250c42951

Author: Eric Anholt <eric at anholt.net>
Date:   Tue Oct 26 14:49:38 2010 -0700

i965: Disable register spilling on gen6 until it's fixed.

Avoids GPU hang on glsl-fs-convolution-1.

---

 src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index d7acc30..bbb210c 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -225,7 +225,7 @@ fs_visitor::assign_regs()
        * loop back into here to try again.
        */
       int reg = choose_spill_reg(g);
-      if (reg == -1) {
+      if (reg == -1 || intel->gen >= 6) {
 	 this->fail = true;
       } else {
 	 spill_reg(reg);