Mesa (master): i965: Always set tiling for depth buffer on sandybridge

[Zhenyu Wang]

Module: Mesa
Branch: master
Commit: 0a1910c26760762eb8d67f68dfd87494ab479e38
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0a1910c26760762eb8d67f68dfd87494ab479e38

Author: Zhenyu Wang <zhenyuw at linux.intel.com>
Date:   Wed Sep 29 13:59:03 2010 +0800

i965: Always set tiling for depth buffer on sandybridge

Sandybridge only support tiling depth buffer, always set tiling bit.

Fix 'fbo_firecube' demo.

---

 src/mesa/drivers/dri/i965/brw_misc_state.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 6eeaba7..7a33412 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -289,7 +289,7 @@ static void emit_depthbuffer(struct brw_context *brw)
       OUT_BATCH(((region->pitch * region->cpp) - 1) |
 		(format << 18) |
 		(BRW_TILEWALK_YMAJOR << 26) |
-		((region->tiling != I915_TILING_NONE) << 27) |
+		(1 << 27) |
 		(BRW_SURFACE_2D << 29));
       OUT_RELOC(region->buffer,
 		I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,