Mesa (master): i965: Change assertion condition from implicit to explicit

[Chad Versace]

Module: Mesa
Branch: master
Commit: d3cc3901ab67823af3aba08efc863daa22ed1408
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d3cc3901ab67823af3aba08efc863daa22ed1408

Author: Chad Versace <chad.versace at intel.com>
Date:   Thu Apr  7 09:09:38 2011 -0700

i965: Change assertion condition from implicit to explicit

... because grokking explicit assertions requires fewer neurons.

In brw_misc_state.c:emit_depthbuffer, change assertion condition
    tiling != I915_TILING_X && tiling != I915_TILING_NONE
to
    tiling == I915_TILING_Y

Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chad Versace <chad.versace at intel.com>

---

 src/mesa/drivers/dri/i965/brw_misc_state.c |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 74e911b..19eea07 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -248,8 +248,7 @@ static void emit_depthbuffer(struct brw_context *brw)
       }
 
       assert(region->tiling != I915_TILING_X);
-      if (intel->gen >= 6)
-	 assert(region->tiling != I915_TILING_NONE);
+      assert(intel->gen < 6 || region->tiling == I915_TILING_Y);
 
       BEGIN_BATCH(len);
       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));