Mesa (7.10): i965: Avoid double-negation of immediate values in the VS.

[Eric Anholt]

Module: Mesa
Branch: 7.10
Commit: 2afa3f47af97d211e21f237c777b1aefb943dd49
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2afa3f47af97d211e21f237c777b1aefb943dd49

Author: Eric Anholt <eric at anholt.net>
Date:   Fri Jan  7 14:26:39 2011 -0800

i965: Avoid double-negation of immediate values in the VS.

In general, we have to negate in immediate values we pass in because
the src1 negate field in the register description is in the bits3 slot
that the 32-bit value is loaded into, so it's ignored by the hardware.
However, the src0 negate field is in bits1, so after we'd negated the
immediate value loaded in, it would also get negated through the
register description.  This broke this VP instruction in the position
calculation in civ4:

MAD TEMP[1], TEMP[1], CONST[256].zzzz, CONST[256].-y-y-y-y;

Bug #30156
(cherry picked from commit 1d1ad6306d0d55b6ba97d9ecc730d5f919d55df5)

---

 src/mesa/drivers/dri/i965/brw_vs_emit.c |    7 +++----
 1 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index 50100d9..0411ce0 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -1426,11 +1426,10 @@ static struct brw_reg get_arg( struct brw_vs_compile *c,
 					  GET_SWZ(src->Swizzle, 1),
 					  GET_SWZ(src->Swizzle, 2),
 					  GET_SWZ(src->Swizzle, 3));
-   }
 
-   /* Note this is ok for non-swizzle instructions: 
-    */
-   reg.negate = src->Negate ? 1 : 0;   
+      /* Note this is ok for non-swizzle ARB_vp instructions */
+      reg.negate = src->Negate ? 1 : 0;
+   }
 
    return reg;
 }