Mesa (master): radeon/r200: fix fbo-clearmipmap + gen-teximage

[Dave Airlie]

Module: Mesa
Branch: master
Commit: f7bab47e6c7cf877acf6d9bb85453851e5aa7f19
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f7bab47e6c7cf877acf6d9bb85453851e5aa7f19

Author: Dave Airlie <airlied at redhat.com>
Date:   Wed Jan 19 10:39:32 2011 +1000

radeon/r200: fix fbo-clearmipmap + gen-teximage

sw clears were being used and not getting the correct offsets in the span
code.

also not emitting correct offsets for CB draws to texture levels.

(I've no idea why I'm playing with r100).

This is a candidate for 7.9 and 7.10

---

 src/mesa/drivers/dri/r200/r200_state_init.c     |    2 +-
 src/mesa/drivers/dri/radeon/radeon_span.c       |    8 ++++----
 src/mesa/drivers/dri/radeon/radeon_state_init.c |    2 +-
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c
index f6afb90..e173cce 100644
--- a/src/mesa/drivers/dri/r200/r200_state_init.c
+++ b/src/mesa/drivers/dri/r200/r200_state_init.c
@@ -587,7 +587,7 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
 
    if (rrb) {
      OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
-     OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
+     OUT_BATCH_RELOC(rrb->draw_offset, rrb->bo, rrb->draw_offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 
      OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
      OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c
index 1c5326f..caf3f25 100644
--- a/src/mesa/drivers/dri/radeon/radeon_span.c
+++ b/src/mesa/drivers/dri/radeon/radeon_span.c
@@ -60,7 +60,7 @@ static void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb);
 static GLubyte *r200_depth_2byte(const struct radeon_renderbuffer * rrb,
 				 GLint x, GLint y)
 {
-    GLubyte *ptr = rrb->bo->ptr;
+    GLubyte *ptr = rrb->bo->ptr + rrb->draw_offset;
     GLint offset;
     if (rrb->has_surface) {
 	offset = x * rrb->cpp + y * rrb->pitch;
@@ -85,7 +85,7 @@ static GLubyte *r200_depth_2byte(const struct radeon_renderbuffer * rrb,
 static GLubyte *r200_depth_4byte(const struct radeon_renderbuffer * rrb,
 				 GLint x, GLint y)
 {
-    GLubyte *ptr = rrb->bo->ptr;
+    GLubyte *ptr = rrb->bo->ptr + rrb->draw_offset;
     GLint offset;
     if (rrb->has_surface) {
 	offset = x * rrb->cpp + y * rrb->pitch;
@@ -439,7 +439,7 @@ static GLubyte *r600_ptr_color(const struct radeon_renderbuffer * rrb,
 static GLubyte *radeon_ptr_4byte(const struct radeon_renderbuffer * rrb,
 			     GLint x, GLint y)
 {
-    GLubyte *ptr = rrb->bo->ptr;
+    GLubyte *ptr = rrb->bo->ptr + rrb->draw_offset;
     uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE;
     GLint offset;
 
@@ -479,7 +479,7 @@ static GLubyte *radeon_ptr_4byte(const struct radeon_renderbuffer * rrb,
 static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
 				     GLint x, GLint y)
 {
-    GLubyte *ptr = rrb->bo->ptr;
+    GLubyte *ptr = rrb->bo->ptr + rrb->draw_offset;
     uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE;
     GLint offset;
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c
index 698efb1..33b504c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state_init.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c
@@ -488,7 +488,7 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
 
    if (rrb) {
      OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
-     OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
+     OUT_BATCH_RELOC(rrb->draw_offset, rrb->bo, rrb->draw_offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 
      OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
      OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);