Mesa (master): i965/fs: Assign URB/ CURB register numbers after instruction scheduling.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 1991d92207cf629ba4ceead4bfc3f768d7b9e402
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1991d92207cf629ba4ceead4bfc3f768d7b9e402

Author: Eric Anholt <eric at anholt.net>
Date:   Tue Jan 18 22:03:34 2011 -0800

i965/fs: Assign URB/CURB register numbers after instruction scheduling.

This fixes a bunch of unnecessary barriers due to the scheduler not
knowing what that arbitrary register description refers to when trying
to reason about its dependencies.

The result is rescheduling in the convolution kernel shader in
Lightsmark, which results in avoiding register spilling and increasing
the performance of the first scene from 6-7 fps midway through the
panning to 11fps.  The register spilling was a regression from Mesa
7.9 to Mesa 7.10.

---

 src/mesa/drivers/dri/i965/brw_fs.cpp |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index c24060b..5f2e9db 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -3681,8 +3681,6 @@ brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c)
 
       v.setup_paramvalues_refs();
       v.setup_pull_constants();
-      v.assign_curb_setup();
-      v.assign_urb_setup();
 
       bool progress;
       do {
@@ -3698,6 +3696,9 @@ brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c)
 
       v.schedule_instructions();
 
+      v.assign_curb_setup();
+      v.assign_urb_setup();
+
       if (0) {
 	 /* Debug of register spilling: Go spill everything. */
 	 int virtual_grf_count = v.virtual_grf_next;