Mesa (master): i965: Convert PIPELINE_SELECT to OUT_BATCH style.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 87de78523ae96737a39267aaa135ddabff05f2f2
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=87de78523ae96737a39267aaa135ddabff05f2f2

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Thu Jun 30 00:05:49 2011 -0700

i965: Convert PIPELINE_SELECT to OUT_BATCH style.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>

---

 src/mesa/drivers/dri/i965/brw_misc_state.c |   14 ++++----------
 1 files changed, 4 insertions(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index a2ee7a5..fcbd97b 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -609,16 +609,10 @@ static void upload_invarient_state( struct brw_context *brw )
    if (intel->gen == 6)
       intel_emit_post_sync_nonzero_flush(intel);
 
-   {
-      /* 0x61040000  Pipeline Select */
-      /*     PipelineSelect            : 0 */
-      struct brw_pipeline_select ps;
-
-      memset(&ps, 0, sizeof(ps));
-      ps.header.opcode = brw->CMD_PIPELINE_SELECT;
-      ps.header.pipeline_select = 0;
-      BRW_BATCH_STRUCT(brw, &ps);
-   }
+   /* Select the 3D pipeline (as opposed to media) */
+   BEGIN_BATCH(1);
+   OUT_BATCH(brw->CMD_PIPELINE_SELECT << 16 | 0);
+   ADVANCE_BATCH();
 
    if (intel->gen < 6) {
       /* Disable depth offset clamping. */