Mesa (master): i965: Add a type argument to brw_state_batch().
Eric Anholt
anholt at kemper.freedesktop.org
Mon Jul 11 16:27:35 UTC 2011
Module: Mesa
Branch: master
Commit: d375df220fae47f38944c4832bcbd5f5d568884c
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d375df220fae47f38944c4832bcbd5f5d568884c
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jun 22 15:14:20 2011 -0700
i965: Add a type argument to brw_state_batch().
I want to make brw_state_dump.c handle more than just the last
statechange, so I want to keep track of what's in the batch state. By
using AUB file numbering for most of these packets, this may be
reusable for aub dumping.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
---
src/mesa/drivers/dri/i965/brw_cc.c | 6 +++-
src/mesa/drivers/dri/i965/brw_clip_state.c | 3 +-
src/mesa/drivers/dri/i965/brw_context.h | 24 +++++++++++++++++++++
src/mesa/drivers/dri/i965/brw_gs_state.c | 3 +-
src/mesa/drivers/dri/i965/brw_sf_state.c | 6 +++-
src/mesa/drivers/dri/i965/brw_state.h | 1 +
src/mesa/drivers/dri/i965/brw_state_batch.c | 1 +
src/mesa/drivers/dri/i965/brw_vs_state.c | 3 +-
src/mesa/drivers/dri/i965/brw_vs_surface_state.c | 3 +-
src/mesa/drivers/dri/i965/brw_wm_sampler_state.c | 9 +++++--
src/mesa/drivers/dri/i965/brw_wm_state.c | 3 +-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 15 ++++++++----
src/mesa/drivers/dri/i965/gen6_cc.c | 6 +++-
src/mesa/drivers/dri/i965/gen6_depthstencil.c | 3 +-
src/mesa/drivers/dri/i965/gen6_scissor_state.c | 3 +-
src/mesa/drivers/dri/i965/gen6_viewport_state.c | 6 +++-
src/mesa/drivers/dri/i965/gen6_vs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen6_wm_state.c | 2 +-
src/mesa/drivers/dri/i965/gen7_sampler_state.c | 3 +-
src/mesa/drivers/dri/i965/gen7_viewport_state.c | 3 +-
src/mesa/drivers/dri/i965/gen7_wm_state.c | 2 +-
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 15 +++++++------
22 files changed, 87 insertions(+), 35 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c
index 94b8c20..9c26150 100644
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -43,7 +43,8 @@ prepare_cc_vp(struct brw_context *brw)
struct gl_context *ctx = &brw->intel.ctx;
struct brw_cc_viewport *ccv;
- ccv = brw_state_batch(brw, sizeof(*ccv), 32, &brw->cc.vp_offset);
+ ccv = brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
+ sizeof(*ccv), 32, &brw->cc.vp_offset);
/* _NEW_TRANSOFORM */
if (ctx->Transform.DepthClamp) {
@@ -98,7 +99,8 @@ static void upload_cc_unit(struct brw_context *brw)
struct gl_context *ctx = &brw->intel.ctx;
struct brw_cc_unit_state *cc;
- cc = brw_state_batch(brw, sizeof(*cc), 64, &brw->cc.state_offset);
+ cc = brw_state_batch(brw, AUB_TRACE_CC_STATE,
+ sizeof(*cc), 64, &brw->cc.state_offset);
memset(cc, 0, sizeof(*cc));
/* _NEW_STENCIL */
diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c
index b9efbb7..31fbadf 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_state.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_state.c
@@ -40,7 +40,8 @@ brw_prepare_clip_unit(struct brw_context *brw)
struct gl_context *ctx = &intel->ctx;
struct brw_clip_unit_state *clip;
- clip = brw_state_batch(brw, sizeof(*clip), 32, &brw->clip.state_offset);
+ clip = brw_state_batch(brw, AUB_TRACE_CLIP_STATE,
+ sizeof(*clip), 32, &brw->clip.state_offset);
memset(clip, 0, sizeof(*clip));
/* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_CLIP_PROG */
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index a8e2b80..012617b 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -188,6 +188,30 @@ struct brw_state_flags {
GLuint cache;
};
+enum state_struct_type {
+ AUB_TRACE_VS_STATE = 1,
+ AUB_TRACE_GS_STATE = 2,
+ AUB_TRACE_CLIP_STATE = 3,
+ AUB_TRACE_SF_STATE = 4,
+ AUB_TRACE_WM_STATE = 5,
+ AUB_TRACE_CC_STATE = 6,
+ AUB_TRACE_CLIP_VP_STATE = 7,
+ AUB_TRACE_SF_VP_STATE = 8,
+ AUB_TRACE_CC_VP_STATE = 0x9,
+ AUB_TRACE_SAMPLER_STATE = 0xa,
+ AUB_TRACE_KERNEL_INSTRUCTIONS = 0xb,
+ AUB_TRACE_SCRATCH_SPACE = 0xc,
+ AUB_TRACE_SAMPLER_DEFAULT_COLOR = 0xd,
+
+ AUB_TRACE_SCISSOR_STATE = 0x15,
+ AUB_TRACE_BLEND_STATE = 0x16,
+ AUB_TRACE_DEPTH_STENCIL_STATE = 0x17,
+
+ /* Not written to .aub files the same way the structures above are. */
+ AUB_TRACE_NO_TYPE = 0x100,
+ AUB_TRACE_BINDING_TABLE = 0x101,
+ AUB_TRACE_SURFACE_STATE = 0x102,
+};
/** Subclass of Mesa vertex program */
struct brw_vertex_program {
diff --git a/src/mesa/drivers/dri/i965/brw_gs_state.c b/src/mesa/drivers/dri/i965/brw_gs_state.c
index bbfefcd..e0309e7 100644
--- a/src/mesa/drivers/dri/i965/brw_gs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_state.c
@@ -41,7 +41,8 @@ brw_prepare_gs_unit(struct brw_context *brw)
struct intel_context *intel = &brw->intel;
struct brw_gs_unit_state *gs;
- gs = brw_state_batch(brw, sizeof(*gs), 32, &brw->gs.state_offset);
+ gs = brw_state_batch(brw, AUB_TRACE_GS_STATE,
+ sizeof(*gs), 32, &brw->gs.state_offset);
memset(gs, 0, sizeof(*gs));
diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index eb3d103..9201be7 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -46,7 +46,8 @@ static void upload_sf_vp(struct brw_context *brw)
const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
const GLfloat *v = ctx->Viewport._WindowMap.m;
- sfv = brw_state_batch(brw, sizeof(*sfv), 32, &brw->sf.vp_offset);
+ sfv = brw_state_batch(brw, AUB_TRACE_SF_VP_STATE,
+ sizeof(*sfv), 32, &brw->sf.vp_offset);
memset(sfv, 0, sizeof(*sfv));
if (render_to_fbo) {
@@ -129,7 +130,8 @@ static void upload_sf_unit( struct brw_context *brw )
int chipset_max_threads;
bool render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
- sf = brw_state_batch(brw, sizeof(*sf), 64, &brw->sf.state_offset);
+ sf = brw_state_batch(brw, AUB_TRACE_SF_STATE,
+ sizeof(*sf), 64, &brw->sf.state_offset);
memset(sf, 0, sizeof(*sf));
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index b384651..cede4e5 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -172,6 +172,7 @@ void brw_destroy_caches( struct brw_context *brw );
sizeof(*(s)), false)
void *brw_state_batch(struct brw_context *brw,
+ enum state_struct_type type,
int size,
int alignment,
uint32_t *out_offset);
diff --git a/src/mesa/drivers/dri/i965/brw_state_batch.c b/src/mesa/drivers/dri/i965/brw_state_batch.c
index 213c7a3..32f315e 100644
--- a/src/mesa/drivers/dri/i965/brw_state_batch.c
+++ b/src/mesa/drivers/dri/i965/brw_state_batch.c
@@ -49,6 +49,7 @@
*/
void *
brw_state_batch(struct brw_context *brw,
+ enum state_struct_type type,
int size,
int alignment,
uint32_t *out_offset)
diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c
index 179ca19..fc4373a 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_state.c
@@ -43,7 +43,8 @@ brw_prepare_vs_unit(struct brw_context *brw)
struct gl_context *ctx = &intel->ctx;
struct brw_vs_unit_state *vs;
- vs = brw_state_batch(brw, sizeof(*vs), 32, &brw->vs.state_offset);
+ vs = brw_state_batch(brw, AUB_TRACE_VS_STATE,
+ sizeof(*vs), 32, &brw->vs.state_offset);
memset(vs, 0, sizeof(*vs));
/* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_VS_PROG */
diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
index 611f633..f9ee4d1 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
@@ -182,7 +182,8 @@ static void upload_vs_surfaces(struct brw_context *brw)
/* Might want to calculate nr_surfaces first, to avoid taking up so much
* space for the binding table. (once we have vs samplers)
*/
- bind = brw_state_batch(brw, sizeof(uint32_t) * BRW_VS_MAX_SURF,
+ bind = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+ sizeof(uint32_t) * BRW_VS_MAX_SURF,
32, &brw->vs.bind_bo_offset);
for (i = 0; i < BRW_VS_MAX_SURF; i++) {
diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
index 5de39aa..9814613 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
@@ -108,7 +108,8 @@ upload_default_color(struct brw_context *brw, struct gl_sampler_object *sampler,
if (intel->gen == 5 || intel->gen == 6) {
struct gen5_sampler_default_color *sdc;
- sdc = brw_state_batch(brw, sizeof(*sdc), 32, &brw->wm.sdc_offset[unit]);
+ sdc = brw_state_batch(brw, AUB_TRACE_SAMPLER_DEFAULT_COLOR,
+ sizeof(*sdc), 32, &brw->wm.sdc_offset[unit]);
memset(sdc, 0, sizeof(*sdc));
@@ -144,7 +145,8 @@ upload_default_color(struct brw_context *brw, struct gl_sampler_object *sampler,
} else {
struct brw_sampler_default_color *sdc;
- sdc = brw_state_batch(brw, sizeof(*sdc), 32, &brw->wm.sdc_offset[unit]);
+ sdc = brw_state_batch(brw, AUB_TRACE_SAMPLER_DEFAULT_COLOR,
+ sizeof(*sdc), 32, &brw->wm.sdc_offset[unit]);
COPY_4V(sdc->color, color);
}
@@ -326,7 +328,8 @@ prepare_wm_samplers(struct brw_context *brw)
if (brw->wm.sampler_count == 0)
return;
- samplers = brw_state_batch(brw, brw->wm.sampler_count * sizeof(*samplers),
+ samplers = brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE,
+ brw->wm.sampler_count * sizeof(*samplers),
32, &brw->wm.sampler_offset);
memset(samplers, 0, brw->wm.sampler_count * sizeof(*samplers));
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index 506e2bd..c820ce4 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -78,7 +78,8 @@ brw_prepare_wm_unit(struct brw_context *brw)
const struct gl_fragment_program *fp = brw->fragment_program;
struct brw_wm_unit_state *wm;
- wm = brw_state_batch(brw, sizeof(*wm), 32, &brw->wm.state_offset);
+ wm = brw_state_batch(brw, AUB_TRACE_WM_STATE,
+ sizeof(*wm), 32, &brw->wm.state_offset);
memset(wm, 0, sizeof(*wm));
if (brw->wm.prog_data->prog_offset_16) {
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 89fea9c..fb4fb14 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -226,7 +226,8 @@ brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
uint32_t *surf;
- surf = brw_state_batch(brw, 6 * 4, 32, &brw->wm.surf_offset[surf_index]);
+ surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+ 6 * 4, 32, &brw->wm.surf_offset[surf_index]);
surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
@@ -272,7 +273,8 @@ brw_create_constant_surface(struct brw_context *brw,
const GLint w = width - 1;
uint32_t *surf;
- surf = brw_state_batch(brw, 6 * 4, 32, out_offset);
+ surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+ 6 * 4, 32, out_offset);
surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
@@ -404,7 +406,8 @@ brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
struct intel_context *intel = &brw->intel;
uint32_t *surf;
- surf = brw_state_batch(brw, 6 * 4, 32, &brw->wm.surf_offset[unit]);
+ surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+ 6 * 4, 32, &brw->wm.surf_offset[unit]);
surf[0] = (BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
@@ -439,7 +442,8 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
uint32_t tile_x, tile_y;
uint32_t format = 0;
- surf = brw_state_batch(brw, 6 * 4, 32, &brw->wm.surf_offset[unit]);
+ surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+ 6 * 4, 32, &brw->wm.surf_offset[unit]);
switch (irb->Base.Format) {
case MESA_FORMAT_XRGB8888:
@@ -637,7 +641,8 @@ brw_wm_upload_binding_table(struct brw_context *brw)
/* Might want to calculate nr_surfaces first, to avoid taking up so much
* space for the binding table.
*/
- bind = brw_state_batch(brw, sizeof(uint32_t) * BRW_WM_MAX_SURF,
+ bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
+ sizeof(uint32_t) * BRW_WM_MAX_SURF,
32, &brw->wm.bind_bo_offset);
for (i = 0; i < BRW_WM_MAX_SURF; i++) {
diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c
index 294d5a5..41d13ad 100644
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -51,7 +51,8 @@ prepare_blend_state(struct brw_context *brw)
nr_draw_buffers = 1;
size = sizeof(*blend) * nr_draw_buffers;
- blend = brw_state_batch(brw, size, 64, &brw->cc.blend_state_offset);
+ blend = brw_state_batch(brw, AUB_TRACE_BLEND_STATE,
+ size, 64, &brw->cc.blend_state_offset);
memset(blend, 0, size);
@@ -139,7 +140,8 @@ gen6_prepare_color_calc_state(struct brw_context *brw)
struct gl_context *ctx = &brw->intel.ctx;
struct gen6_color_calc_state *cc;
- cc = brw_state_batch(brw, sizeof(*cc), 64, &brw->cc.state_offset);
+ cc = brw_state_batch(brw, AUB_TRACE_CC_STATE,
+ sizeof(*cc), 64, &brw->cc.state_offset);
memset(cc, 0, sizeof(*cc));
/* _NEW_COLOR */
diff --git a/src/mesa/drivers/dri/i965/gen6_depthstencil.c b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
index 775e1ce..5d14147 100644
--- a/src/mesa/drivers/dri/i965/gen6_depthstencil.c
+++ b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
@@ -34,7 +34,8 @@ gen6_prepare_depth_stencil_state(struct brw_context *brw)
struct gl_context *ctx = &brw->intel.ctx;
struct gen6_depth_stencil_state *ds;
- ds = brw_state_batch(brw, sizeof(*ds), 64,
+ ds = brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE,
+ sizeof(*ds), 64,
&brw->cc.depth_stencil_state_offset);
memset(ds, 0, sizeof(*ds));
diff --git a/src/mesa/drivers/dri/i965/gen6_scissor_state.c b/src/mesa/drivers/dri/i965/gen6_scissor_state.c
index 7492e50..dc73b10 100644
--- a/src/mesa/drivers/dri/i965/gen6_scissor_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_scissor_state.c
@@ -39,7 +39,8 @@ gen6_upload_scissor_state(struct brw_context *brw)
struct gen6_scissor_rect *scissor;
uint32_t scissor_state_offset;
- scissor = brw_state_batch(brw, sizeof(*scissor), 32, &scissor_state_offset);
+ scissor = brw_state_batch(brw, AUB_TRACE_SCISSOR_STATE,
+ sizeof(*scissor), 32, &scissor_state_offset);
/* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
diff --git a/src/mesa/drivers/dri/i965/gen6_viewport_state.c b/src/mesa/drivers/dri/i965/gen6_viewport_state.c
index c6c55c9..a4bfa54 100644
--- a/src/mesa/drivers/dri/i965/gen6_viewport_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_viewport_state.c
@@ -43,7 +43,8 @@ prepare_clip_vp(struct brw_context *brw)
{
struct brw_clipper_viewport *vp;
- vp = brw_state_batch(brw, sizeof(*vp), 32, &brw->clip.vp_offset);
+ vp = brw_state_batch(brw, AUB_TRACE_CLIP_VP_STATE,
+ sizeof(*vp), 32, &brw->clip.vp_offset);
vp->xmin = -1.0;
vp->xmax = 1.0;
@@ -72,7 +73,8 @@ prepare_sf_vp(struct brw_context *brw)
const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
const GLfloat *v = ctx->Viewport._WindowMap.m;
- sfv = brw_state_batch(brw, sizeof(*sfv), 32, &brw->sf.vp_offset);
+ sfv = brw_state_batch(brw, AUB_TRACE_SF_VP_STATE,
+ sizeof(*sfv), 32, &brw->sf.vp_offset);
memset(sfv, 0, sizeof(*sfv));
/* _NEW_BUFFERS */
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 022e23e..ecdf5e4 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -60,7 +60,7 @@ gen6_prepare_vs_push_constants(struct brw_context *brw)
float *param;
int i;
- param = brw_state_batch(brw,
+ param = brw_state_batch(brw, AUB_TRACE_NO_TYPE,
(MAX_CLIP_PLANES + nr_params) *
4 * sizeof(float),
32, &brw->vs.push_const_offset);
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index 9ef6133..185da9c 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -54,7 +54,7 @@ gen6_prepare_wm_push_constants(struct brw_context *brw)
float *constants;
unsigned int i;
- constants = brw_state_batch(brw,
+ constants = brw_state_batch(brw, AUB_TRACE_NO_TYPE,
brw->wm.prog_data->nr_params *
sizeof(float),
32, &brw->wm.push_const_offset);
diff --git a/src/mesa/drivers/dri/i965/gen7_sampler_state.c b/src/mesa/drivers/dri/i965/gen7_sampler_state.c
index 95f6fbf..e787c21 100644
--- a/src/mesa/drivers/dri/i965/gen7_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sampler_state.c
@@ -183,7 +183,8 @@ gen7_prepare_samplers(struct brw_context *brw)
if (brw->wm.sampler_count == 0)
return;
- samplers = brw_state_batch(brw, brw->wm.sampler_count * sizeof(*samplers),
+ samplers = brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE,
+ brw->wm.sampler_count * sizeof(*samplers),
32, &brw->wm.sampler_offset);
memset(samplers, 0, brw->wm.sampler_count * sizeof(*samplers));
diff --git a/src/mesa/drivers/dri/i965/gen7_viewport_state.c b/src/mesa/drivers/dri/i965/gen7_viewport_state.c
index 838ad3a..e9aacd5 100644
--- a/src/mesa/drivers/dri/i965/gen7_viewport_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_viewport_state.c
@@ -36,7 +36,8 @@ prepare_sf_clip_viewport(struct brw_context *brw)
const GLfloat *v = ctx->Viewport._WindowMap.m;
struct gen7_sf_clip_viewport *vp;
- vp = brw_state_batch(brw, sizeof(vp), 64, &brw->sf.vp_offset);
+ vp = brw_state_batch(brw, AUB_TRACE_SF_VP_STATE,
+ sizeof(vp), 64, &brw->sf.vp_offset);
/* Also assign to clip.vp_offset in case something uses it. */
brw->clip.vp_offset = brw->sf.vp_offset;
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 0f5b06c..a102ca7 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -51,7 +51,7 @@ gen7_prepare_wm_constants(struct brw_context *brw)
float *constants;
unsigned int i;
- constants = brw_state_batch(brw,
+ constants = brw_state_batch(brw, AUB_TRACE_NO_TYPE,
brw->wm.prog_data->nr_params *
sizeof(float),
32, &brw->wm.push_const_offset);
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 9994b67..4add1a6 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -65,8 +65,8 @@ gen7_update_texture_surface(struct gl_context *ctx, GLuint unit)
const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
struct gen7_surface_state *surf;
- surf = brw_state_batch(brw, sizeof(*surf), 32,
- &brw->wm.surf_offset[surf_index]);
+ surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+ sizeof(*surf), 32, &brw->wm.surf_offset[surf_index]);
memset(surf, 0, sizeof(*surf));
surf->ss0.surface_type = translate_tex_target(tObj->Target);
@@ -135,7 +135,8 @@ gen7_create_constant_surface(struct brw_context *brw,
const GLint w = width - 1;
struct gen7_surface_state *surf;
- surf = brw_state_batch(brw, sizeof(*surf), 32, out_offset);
+ surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+ sizeof(*surf), 32, out_offset);
memset(surf, 0, sizeof(*surf));
surf->ss0.surface_type = BRW_SURFACE_BUFFER;
@@ -210,8 +211,8 @@ gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
{
struct gen7_surface_state *surf;
- surf = brw_state_batch(brw, sizeof(*surf), 32,
- &brw->wm.surf_offset[unit]);
+ surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+ sizeof(*surf), 32, &brw->wm.surf_offset[unit]);
memset(surf, 0, sizeof(*surf));
surf->ss0.surface_type = BRW_SURFACE_NULL;
@@ -235,8 +236,8 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
struct gen7_surface_state *surf;
uint32_t tile_x, tile_y;
- surf = brw_state_batch(brw, sizeof(*surf), 32,
- &brw->wm.surf_offset[unit]);
+ surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+ sizeof(*surf), 32, &brw->wm.surf_offset[unit]);
memset(surf, 0, sizeof(*surf));
switch (irb->Base.Format) {
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