Mesa (master): i965: Emit texture cache flushes on gen6 along with render cache flushes.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 185868c9c2e6a31a7313df2dbe29490547b65f61
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=185868c9c2e6a31a7313df2dbe29490547b65f61

Author: Eric Anholt <eric at anholt.net>
Date:   Mon Jul 25 11:50:27 2011 -0700

i965: Emit texture cache flushes on gen6 along with render cache flushes.

It turns out that internally the texture cache gets flushed in a
couple of cases, particularly around 2D operations mixed with 3D.  In
almost all cases one of those happens between rendering to an
FBO-attached texture and rendering from that texture.  However, as of
the next patch, glean tfbo (and the new fbo-flushing-2 test) would
manage to get stale texture values because one of those flushes didn't
occur.  The intention of this code was always to get the render cache
cleared and ready to be used from the sampler cache (and it does on <=
gen4), so this just catches gen5 up.

This patch was also tested to fix fbo-flushing on gen7.

---

 src/mesa/drivers/dri/intel/intel_batchbuffer.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index 97cc219..db4343b 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -390,6 +390,7 @@ intel_batchbuffer_emit_mi_flush(struct intel_context *intel)
 	 OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
 		   PIPE_CONTROL_WRITE_FLUSH |
 		   PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+		   PIPE_CONTROL_TC_FLUSH |
 		   PIPE_CONTROL_NO_WRITE);
 	 OUT_BATCH(0); /* write address */
 	 OUT_BATCH(0); /* write data */