Mesa (master): intel: Unobfuscate intel_alloc_renderbuffer_storage
Chad Versace
chadversary at kemper.freedesktop.org
Tue Jun 21 18:36:03 UTC 2011
Module: Mesa
Branch: master
Commit: 36e05c6870fc466053b4f54edd890e19d5ac9dcf
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=36e05c6870fc466053b4f54edd890e19d5ac9dcf
Author: Chad Versace <chad at chad-versace.us>
Date: Tue Jun 14 17:38:30 2011 -0700
intel: Unobfuscate intel_alloc_renderbuffer_storage
Hiz buffer allocation can only occur if the 'else' branch has been taken,
so move the hiz buffer allocation into the 'else' branch.
Having the hiz buffer allocation dangling outside of the if-tree was just
damn confusing.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chad Versace <chad at chad-versace.us>
---
src/mesa/drivers/dri/intel/intel_fbo.c | 34 ++++++++++++++++----------------
1 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index b48eac4..ff09b5d 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -196,26 +196,26 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer
width,
height / 2,
GL_TRUE);
+ if (!irb->region)
+ return false;
+
} else {
irb->region = intel_region_alloc(intel->intelScreen, tiling, cpp,
width, height, GL_TRUE);
- }
-
- if (!irb->region)
- return GL_FALSE; /* out of memory? */
-
- ASSERT(irb->region->buffer);
-
- if (intel->vtbl.is_hiz_depth_format(intel, rb->Format)) {
- irb->hiz_region = intel_region_alloc(intel->intelScreen,
- I915_TILING_Y,
- irb->region->cpp,
- irb->region->width,
- irb->region->height,
- GL_TRUE);
- if (!irb->hiz_region) {
- intel_region_release(&irb->region);
- return GL_FALSE;
+ if (!irb->region)
+ return false;
+
+ if (intel->vtbl.is_hiz_depth_format(intel, rb->Format)) {
+ irb->hiz_region = intel_region_alloc(intel->intelScreen,
+ I915_TILING_Y,
+ irb->region->cpp,
+ irb->region->width,
+ irb->region->height,
+ GL_TRUE);
+ if (!irb->hiz_region) {
+ intel_region_release(&irb->region);
+ return false;
+ }
}
}
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