Mesa (master): i965/fs: Fix GPU hang on texture2d-bias on pre-Ironlake.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 4bbc7915f16a8b0dcead3f34aa1b4f0328147bea
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4bbc7915f16a8b0dcead3f34aa1b4f0328147bea

Author: Eric Anholt <eric at anholt.net>
Date:   Thu May 12 08:49:53 2011 -0700

i965/fs: Fix GPU hang on texture2d-bias on pre-Ironlake.

In the 16-wide rework, I missed that we were setting some things to be
SIMD16 mode (corresponding to their setup in emit_texture_gen4()).

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

---

 src/mesa/drivers/dri/i965/brw_fs.cpp |   11 +++++++----
 1 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 1943ab6..75454be 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -2531,11 +2531,8 @@ fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
    int rlen = 4;
    uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
 
-   if (c->dispatch_width == 16) {
-      rlen = 8;
-      dst = vec16(dst);
+   if (c->dispatch_width == 16)
       simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
-   }
 
    if (intel->gen >= 5) {
       switch (inst->opcode) {
@@ -2570,6 +2567,7 @@ fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
 	 /* Note that G45 and older determines shadow compare and dispatch width
 	  * from message length for most messages.
 	  */
+	 assert(c->dispatch_width == 8);
 	 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
 	 if (inst->shadow_compare) {
 	    assert(inst->mlen == 6);
@@ -2604,6 +2602,11 @@ fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
    }
    assert(msg_type != -1);
 
+   if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
+      rlen = 8;
+      dst = vec16(dst);
+   }
+
    brw_SAMPLE(p,
 	      retype(dst, BRW_REGISTER_TYPE_UW),
 	      inst->base_mrf,