Mesa (master): radeon/r200: fix r100/r200 blit to use the offsets.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 71f1d468b4e183c45e4f76f7951beb44dd74a707
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=71f1d468b4e183c45e4f76f7951beb44dd74a707

Author: Dave Airlie <airlied at redhat.com>
Date:   Fri Nov  4 17:12:02 2011 +0000

radeon/r200: fix r100/r200 blit to use the offsets.

This is needed to do proper renderbuffer operation on mipmaps.

Signed-off-by: Dave Airlie <airlied at redhat.com>

---

 src/mesa/drivers/dri/r200/r200_blit.c     |    4 ++--
 src/mesa/drivers/dri/radeon/radeon_blit.c |    4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/r200/r200_blit.c b/src/mesa/drivers/dri/r200/r200_blit.c
index 05a15c4..487bb5b 100644
--- a/src/mesa/drivers/dri/r200/r200_blit.c
+++ b/src/mesa/drivers/dri/r200/r200_blit.c
@@ -278,7 +278,7 @@ static void inline emit_tx_setup(struct r200_context *r200,
     OUT_BATCH_REGVAL(R200_PP_TXPITCH_0, pitch * _mesa_get_format_bytes(src_mesa_format) - 32);
 
     OUT_BATCH_REGSEQ(R200_PP_TXOFFSET_0, 1);
-    OUT_BATCH_RELOC(0, bo, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
+    OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 
     END_BATCH();
 }
@@ -332,7 +332,7 @@ static inline void emit_cb_setup(struct r200_context *r200,
     OUT_BATCH_REGVAL(RADEON_RB3D_CNTL, dst_format);
 
     OUT_BATCH_REGSEQ(RADEON_RB3D_COLOROFFSET, 1);
-    OUT_BATCH_RELOC(0, bo, 0, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
+    OUT_BATCH_RELOC(offset, bo, offset, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
     OUT_BATCH_REGSEQ(RADEON_RB3D_COLORPITCH, 1);
     OUT_BATCH_RELOC(dst_pitch, bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_blit.c b/src/mesa/drivers/dri/radeon/radeon_blit.c
index fe14540..25d2119 100644
--- a/src/mesa/drivers/dri/radeon/radeon_blit.c
+++ b/src/mesa/drivers/dri/radeon/radeon_blit.c
@@ -156,7 +156,7 @@ static void inline emit_tx_setup(struct r100_context *r100,
     OUT_BATCH_REGVAL(RADEON_PP_TEX_PITCH_0, pitch * _mesa_get_format_bytes(mesa_format) - 32);
 
     OUT_BATCH_REGSEQ(RADEON_PP_TXOFFSET_0, 1);
-    OUT_BATCH_RELOC(0, bo, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
+    OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 
     END_BATCH();
 }
@@ -206,7 +206,7 @@ static inline void emit_cb_setup(struct r100_context *r100,
     OUT_BATCH_REGVAL(RADEON_RB3D_CNTL, dst_format);
 
     OUT_BATCH_REGSEQ(RADEON_RB3D_COLOROFFSET, 1);
-    OUT_BATCH_RELOC(0, bo, 0, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
+    OUT_BATCH_RELOC(offset, bo, offset, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
     OUT_BATCH_REGSEQ(RADEON_RB3D_COLORPITCH, 1);
     OUT_BATCH_RELOC(dst_pitch, bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);