Mesa (master): 42 new commits
Chad Versace
chadversary at kemper.freedesktop.org
Tue Nov 22 18:52:47 UTC 2011
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4ce635c871d00e442efb2b265562685d7edd44ae
Merge: 1f3c5eae5c4be582e50c2d4d7950424d86059c45 e5411d8fdc6a7dda18d82746b84197ef83ee0a13
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Tue Nov 22 10:52:29 2011 -0800
Merge branch 'hiz' of ssh://people.freedesktop.org/~chadversary/mesa
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5411d8fdc6a7dda18d82746b84197ef83ee0a13
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Thu Nov 17 08:53:39 2011 -0800
i965/gen6: Enable HiZ by default
Regresses one Piglit test: bugs/fdo10370.
I'm not enabling HiZ for gen7 yet because it causes a mysterious
performance regression.
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b18875d441ca4b7b1a4098659fb4298a4bf265f6
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Thu Nov 17 08:50:05 2011 -0800
intel: Use separate stencil whenever possible
For depthstencil renderbuffers, we were using separate stencil only if the
hardware required it. Since the performance gains from HiZ is so high, we
should always use separate stencil if the hardware supports it.
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e7e81714f3ecf67a975d35e74bdb7fd15d924e4d
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 7 15:58:43 2011 -0800
i965: Implement the actual tables for texture alignment units [v2]
I implemented functions for horizontal/vertical alignment units separately
because I find it easier to read that way...especially with all the
corner-cases.
[chad] Corrected the vertical alignment calculation by checking for
depthstencil formats.
v2:
- Fix typos in intel_horizontal_texture_alignment_unit():
s/height/width/ and s/VALIGN/HALIGN.
- Remove special case for compressed formats in
intel_get_texture_alignment unit(). Compressed formats are already
handled in the halign and valign functions.
- Replace check ``_mesa_is_depth_format(...) ||
_mesa_is_depthstencil_format(...)`` with explcitit checks against
GL_DEPTH_COMPONENT and GL_DEPTH_STENCIL.
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dd0e46c4102976b7d317104ecd1bb565ac34613a
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Thu Nov 17 09:09:56 2011 -0800
i965/gen6: Set vertical alignment in SURFACE_STATE batch
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=017c13d55b5b086774d6afea2ca754482c624c6a
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Thu Nov 17 08:30:30 2011 -0800
intel: Store miptree alignment units in the miptree
This allows us to replace all the calls to
intel_get_texture_alignment_unit() with a single call at miptree creation.
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=293e9a7ccfeb64efd54464658518e4ded054a13c
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Tue Nov 15 22:51:35 2011 -0800
intel: Enable HiZ for texture renderbuffers
When a depth texture is first attached to framebuffer, allocate a HiZ
miptree for it.
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b264698d30d3c789bbe1fc64fd72c731f342877a
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Tue Nov 15 18:25:39 2011 -0800
intel: Resolve buffers in intel_map_renderbuffer()
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d2e35a5460c5c4b3951c0aaca4fdb867b20478bb
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Tue Nov 15 18:21:12 2011 -0800
intel: Resolve buffers in intel_map_texture_image()
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d760664e6349c72624aa6d54d40df0233995c8e
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Tue Nov 15 18:21:09 2011 -0800
intel: Mark needed resolves when first enabling HiZ on a miptree
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b2baf3b08d545c772e9636fb0a0614c489c3916
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Tue Nov 15 18:20:43 2011 -0800
i965: Mark that depth buffer needs depth resolve after drawing
After brw_try_draw_prims() emits a batch, mark that the depth buffer needs
a depth resolve if the buffer was written to and if it has an accompanying
HiZ buffer.
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=622bae07a5da91bc966d173fd6df92a640e4f574
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Tue Nov 15 18:21:05 2011 -0800
intel: Resolve buffers in intelSpanRenderStart
Resolve all buffers that will be mapped by intelSpanRenderStart. This
comprises resolving the depth buffer of each enabled texture and of the
read and draw buffers.
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1eede4aa8771c058bc560123d4b7c5625e23c8b6
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Tue Nov 15 18:20:57 2011 -0800
intel: Refactor intelSpanRenderStart
Factor the mapping loops from intelSpanRenderStart() into
intel_span_map_buffers(). This in preparation for the next commit,
which resolves the buffers before mapping.
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b0d295e122f8ca6e0ebe4593a1e0660308a18c3
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Tue Nov 15 18:20:39 2011 -0800
i965: Resolve buffers before drawing [v2]
Before emitting primitives in brw_try_draw_prims(), resolve the depth
buffer's HiZ buffer and resolve the depth buffer of each enabled depth
texture.
v2: [anholt] The driver no longer validates drm bo's, so update a comment
to reflect that.
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b95986729ef3522a65b7357aea99c6358f9d53c8
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Tue Nov 15 18:20:34 2011 -0800
i965: Prevent recursive calls to FLUSH_VERTICES [v2]
To do so, we must resolve all buffers on entering a glBegin/glEnd block.
For the detailed explanation, see the Doxygen comments in this patch.
v2:
- Fix typo: s/enusure/ensure/.
- In brwPrepareExecBegin(), do the same resolves as done by
brw_predraw_resolve_buffers().
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=12498553462c7807034814cf843d86d52c407380
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Tue Nov 15 18:20:31 2011 -0800
i965/gen6: Manipulate state batches for HiZ meta-ops [v4]
A lot of the state manipulation is handled by the meta-op state setup.
However, some batches need manual intervention.
v2:
Do not special-case the 3DSTATE_DEPTH_STENCIL.Depth_Test_Enable bit
for HiZ in gen6_upload_depth_stencil(). The HiZ meta-op sets
ctx->Depth.Test, just read the value from that.
v3:
Add a new dirty flag, BRW_STATE_HIZ, for brw_tracked_state. Flag it
immediately before and after executing the HiZ operation in
gen6_resolve_slice(). Add the flag to the the dirty bits for the
following state packets:
gen6_clip_state
gen6_depth_stencil_state
gen6_sf_state
gen6_wm_state
v4:
- Add BRW_NEW_STATE_HIZ to the dirty bit table in brw_state_upload.c.
This is needed for INTEL_DEBUG=state.
- Align brw dirty bit for gen6_depth_stencil_state.
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1f1d348d8ff6ce9249cd9971e79e5bce0e60756
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Thu Nov 17 08:10:57 2011 -0800
i965/gen6: Complete stubs for HiZ buffer resolves
Some state batches also need to be manipulated. That's done in the next
commit.
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=77a18428fffc938a4e3fa9b592e3e104dda0fe7f
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Tue Nov 15 18:20:20 2011 -0800
i965: Add HiZ operation state to brw_context
brw_context::hiz contains state needed to perform HiZ meta-ops and
indicates if a HiZ operation is currently in progress.
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1383e56bd916f9fc4357a6224aac4e8c691303cb
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Thu Nov 17 08:03:48 2011 -0800
intel: Add resolve functions for renderbuffers
Add the following functions:
intel_renderbuffer_resolve_hiz
intel_renderbuffer_resolve_depth
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2945abea338031cbe90665df60152982bfca6177
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Tue Nov 15 18:20:02 2011 -0800
intel: Add resolve functions for miptrees
Add functions that
- set a miptree slice as needing a resolve
- resolve a single slice of a miptree
- resolve all slices of a miptree
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cf5e08c8e41473467a8732fc834cec52f8b10dc8
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Thu Nov 17 07:42:21 2011 -0800
intel: Add field intel_mipmap_tree::hiz_map
This is a map of miptree slices to needed resolves.
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8d3aa14e893d2912c393ac1ad9e142699d561018
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Wed Nov 16 23:43:56 2011 -0800
intel: Define struct intel_resolve_map [v2]
This is a map of miptree slices to needed resolves, implemented as
a linked list. A future commit will embed such a list in
intel_mipmap_tree.
If you think I'm crazy to put a list in a miptree, read the Doxygen in
this patch for intel_resolve_map.
v2: [anholt] Move Doxygen from functin prototypes to definitions.
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f17b12278dcc0e370d04a2a9a73677ab4c9f2c26
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Wed Nov 16 23:23:30 2011 -0800
intel: Change signature of HiZ resolve functions
Now that intel_renderbuffer::region has been replaced with a miptree, the
HiZ functions region parameter must be replaced with a miptree parameter.
Change the return type from bool to void.
Rename the 'depth' parameter to 'layer', because it will correspond to
irb->mt_layer.
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c0151839473c83a2d0eea6285a649c1674466752
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Wed Nov 16 23:10:48 2011 -0800
intel: Remove unused HiZ functions
Remove the following functions:
i830_hiz_resolve_noop
i915_hiz_resolve_noop
brw_hiz_resolve_noop
My original strategy for how intel->vtbl.resolve_*buffer was used has
substantially changed. The above functions are no longer called in the
current strategy.
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a2e44b0813e956440c451c107cf5564b56cbe98e
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Wed Nov 16 23:14:39 2011 -0800
intel: Replace intel_mipmap_tree::hiz_region with a miptree [v2]
This is required to correctly implement HiZ for mipmapped and
multi-layered textures.
v2: Accomodate refcount fixes in intel_process_dri2_buffer_*() that were
introduced in v2 of commit
intel: Replace intel_renderbuffer::region with a miptree [v2]
Reviewed-by: Eric Anholt <eric at anholt>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3eb12dfaeed03f77e31943eea164acb03e86bbc9
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Tue Nov 15 22:17:34 2011 -0800
intel: Replace intel_texture_image::stencil_irb with intel_mipmap_tree::stencil_mt [v3]
For depthstencil textures using separate stencil, we embedded a stencil
buffer in intel_texture_image. The intention was that the embedded stencil
buffer would be the golden copy of the texture's stencil bits. When
necessary, we scattered/gathered the stencil bits between the texture
miptree and the embedded stencil buffer.
This approach had a serious deficiency for mipmapped or multi-layer
textures. Any given moment the embedded stencil buffer was consistent with
exactly one miptree slice, the most recent one to be scattered. This
permitted tests of type A to pass, but broke tests of type B.
Test A:
1. Create a depthstencil texture.
2. Upload data into (level=x1,layer=y1).
3. Read and test stencil data at (level=x1, layer=y1).
4. Upload data into (level=x2,layer=y2).
5. Read and test stencil data at (level=x2, layer=y2).
Test B:
1. Create a depthstencil texture.
2. Upload data into (level=x1,layer=y1).
3. Upload data into (level=x2,layer=y2).
4. Read and test stencil data at (level=x1, layer=y1).
5. Read and test stencil data at (level=x2, layer=y2).
v2:
Only allocate stencil miptree if intel->must_use_separate_stencil,
because we don't make the conversion from must_use_separate_stencil to
has_separate_stencil until commit
intel: Use separate stencil whenever possible
v3:
Don't call ChooseNewTexture in intel_renderbuffer_wrap_miptree() in
order to determine the renderbuffer format. Instead, pass the format as
a param to that function.
CC: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c80b31fdee1fa96b8d45ad2537ecdb5b9151973e
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Tue Nov 15 22:11:33 2011 -0800
intel: Refactor intel_render_texture() [v2]
This is in preparation for properly implementing glFramebufferTexture*()
for mipmapped depthstencil textures. The FIXME comments deleted by this
patch give a rough explanation of what was broken.
This refactor does the following:
- In intel_update_wrapper() and intel_wrap_texture(), change the
parameters to prepare to remove functions' dependency on
gl_texture_image.
- Move the call to intel_renderbuffer_set_draw_offsets() from
intel_render_texture() into intel_udpate_wrapper().
Each time I encounter those functions, I dislike their vague names.
(Update which wrapper? What is wrapped? What is the wrapper?). So, while
I was mucking around, I also renamed the functions.
v2:
In addition to the ``GLenum internal_format`` parameter to
intel_wrap_miptree(), add a ``gl_format format`` parameter. This
removes the need to recalculate for the true format from
internal_format with ChooseNewTextureFormat, which was just weird.
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=73540690f71280a2bdda51b45203fd4ed43a1760
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Wed Nov 16 22:42:44 2011 -0800
intel: Define intel_miptree_check_level_layer()
This is a small helper function that asserts that a given level and layer
are valid for a miptree. I will be extensively using it in the future
miptree HiZ functions.
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b38b33c1648b07e75dc4d8340758171e109c598
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Tue Nov 15 10:22:14 2011 -0800
intel: Remove unneeded params from intel_renderbuffer_set_draw_offset()
Since the renderbuffer tracks the miptree level and layer that it wraps,
the 'tex_image' and 'zoffset' params are no longer needed to calculate the draw
offsets.
Not only are they no longer needed, but their presence would prevent
calculating the renderbuffer draw offsets in situations where there were
no texture image. Such situations will occur during the HiZ meta-op and
during scatter/gather of separate stencil textures.
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=24da7335b22432ef4c2d57cab86e4b8fbe8733d5
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Tue Nov 15 10:05:21 2011 -0800
intel: Track the miptree layer wrapped by a renderbuffer [v2]
TODO: Make v2 for kwg.
Add two fields to intel_renderbuffer:
mt_level
mt_layer
Multiple renderbuffers may simultaneously wrap a single texture and each
provide a different view into that texture. [Consider
glFramebufferTextureLayer()]. The new fields indicate which slice of the
miptree is wrapped by the renderbuffer.
The buffer resolve operations, to be introduced in the future, require
these fields in order to resolve the correct slice in the miptree.
To add the fields, it was necessary to replace the type of some function
parameters from gl_texture_image to gl_renderbuffer_attachment.
v2: [kwg] Replace confusing condition `CubeMapFace > 0` with the more
sensible `Target == GL_TEXTURE_CUBE_MAP`.
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d7b33309fe160212f2eb73f471f3aedcb5d0b5c1
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Tue Nov 15 09:55:40 2011 -0800
intel: Kill intel_mipmap_level::nr_images [v4]
For all texture targets except GL_TEXTURE_CUBE_MAP, the 'nr_images' and
'depth' fields of intel_mipmap_level were identical. In the exceptional
case, nr_images == 6 and depth == 1.
It is simple to determine if a texture is a cube or not, so the presence
of two fields here was not helpful. Worse, it was confusing. When we
eventually implement GL_ARB_texture_cube_map_array, this mess would have
become even more confusing.
This patch removes 'nr_images' and assigns to 'depth' a consistent
meaning: depth is the number of 2D slices at each miplevel. The exact
semantics of depth varies according to the texture target:
- For GL_TEXTURE_CUBE_MAP, depth is 6.
- For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
identical for all miplevels in the texture.
- For GL_TEXTURE_3D, it is the texture's depth at each miplevel. Its
value, like width and height, varies with miplevel.
- For other texture types, depth is 1.
As a consequence, parameters were removed from the following function
signatures:
intel_miptree_set_level_info
Remove 'nr_images'.
i945_miptree_layout
brw_miptree_layout_texture
brw_miptree_layout_texture_array
Remove 'slices'.
v2:
- Replace "It's" with "Its".
- Remove all hunks in intel_fbo.c. The hunks were spurious and sneaked
in during a rebase.
- Remove unneeded hunk in intel_tex_map_image_for_swrast(). It was
a little refactor of the for-loop's upper bound.
v4:
In intel_miptree_get_image_offset(), document the conditions under
which different if-branches are taken.
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=278e77a1192d5251c5b70a555e676f72b446e8e1
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Wed Nov 16 22:26:38 2011 -0800
intel: Refactor intel_miptree_copy_teximage()
Extract the body of the inner loop into a new function,
intel_miptree_copy_slice().
This is in preparation for adding support for separate stencil and HiZ to
intel_miptree_copy_teximage(). When copying a slice of a depthstencil
miptree that uses separate stencil, we will also need to copy the
corresponding slice of the stencil miptree. The easiest way to do this
will be to call intel_miptree_copy_slice() recursively. Analogous
reasoning applies to copying a slice of a depth miptree with HiZ.
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2ddde70daece24d1eb7185946032158993a9e4d
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Mon Nov 14 08:56:26 2011 -0800
intel: Refactor intel_mipmap_level offsets
Add a new field, intel_mipmap_level::slice, and move the offset fields
into it. Also add some much needed documentation for these fields.
Before this patch, a separate array was allocated for the
intel_mipmap_level::{x,y}_offsets. This was just silly; it incurred an
extra call to malloc and diminished memory locality.
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=da2816a45e6e3a33246a341fee72e6f893f315d9
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Wed Nov 16 14:04:25 2011 -0800
intel: Replace intel_renderbuffer::region with a miptree [v3]
Essentially, this patch just globally substitutes `irb->region` with
`irb->mt->region` and then does some minor cleanups to avoid segfaults
and other problems.
This is in preparation for
1. Fixing scatter/gather for mipmapped separate stencil textures.
2. Supporting HiZ for mipmapped depth textures.
As a nice benefit, this lays down some preliminary groundwork for easily
texturing from any renderbuffer, even those of the window system.
A future commit will replace intel_mipmap_tree::hiz_region with a miptree.
v2:
- Return early in intel_process_dri2_buffer_*() if region allocation
fails.
- Fix double semicolon.
- Fix miptree reference leaks in the following functions:
intel_process_dri2_buffer_with_separate_stencil()
intel_image_target_renderbuffer_storage()
v3:
- [anholt] Fix check for hiz allocation failure. Replace
``if (!irb->mt)` with ``if(!irb->mt->hiz_region)``.
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=005149d5860ad55c5e58e2de8a138e3a763f2036
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Sun Nov 13 23:04:24 2011 -0800
intel: Define intel_miptree_create_for_renderbuffer()
This function creates a miptree that is suitable as storage for
a non-texture renderbuffer.
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c3c7cbd15418293208034e8970d626b5998abd4b
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Sun Nov 13 23:06:17 2011 -0800
intel: Move inline functions from intel_fbo.h to .c
Move the following inline functions:
intel_get_rb_region
intel_framebuffer_has_hiz
A future commit will replace the renderbuffer's region with a miptree.
This small refactor will eliminate the need for intel_fbo.h to include
intel_mipmap_tree.h on that commit. I'd like to avoid the situation where
each header transitively includes every other header.
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=19faa12bb751eabc1590d042adbd345b89542de0
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Sun Nov 13 23:05:47 2011 -0800
intel: Kill intel_framebuffer_get_hiz_region()
The only user of intel_framebuffer_get_hiz_region() was
intel_framebuffer_has_hiz(). So I folded the body of the former into the
latter.
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e9b3c098c58af49a809afbc17d508f23eab21c2
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Sun Nov 13 23:02:04 2011 -0800
intel: Temporarily disable HiZ for textures
A great refactor thrashing begins after this commit for HiZ and separate
stencil. Removing code for texture HiZ will make that refactoring easier,
because then we don't have to maintain that code during the refactor.
To disable HiZ for textures, I've removed the hook in
intel_update_wrapper() that allocates a HiZ buffer when attaching a depth
texture to a framebuffer.
HiZ was broken for textures anyway, so there's no regression here.
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=190aec75a4362b56b9b311975a777c56e8e6c67d
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Wed Nov 16 16:02:39 2011 -0800
intel: Always gather stencil buffer in intel_map_renderbuffer_separate_s8z24()
The function gathered the stencil buffer into the depth buffer only when
the map mode contained the read bit. But we must do the gather even if the
map mode is write-only. If we do not, then, when the depth buffer's stencil
bits are scattered into the stencil buffer by intel_unmap_renderbuffer(),
some of the scattered stencil bits would be invalid.
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=af35a3523df7f555427de4835ae092d1836c3c95
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Sun Nov 13 17:45:51 2011 -0800
intel: Fix swrast_render_start() for depthstencil buffers with separate stencil
1. Don't map the depthstencil buffer twice
Place a guard in intel_renderbuffer_map() to prevent a renderbuffer
from being mapped twice. This happened if a single buffer was attached to
the framebuffer's depth and stencil attachment points. (Interestingly,
because intel_map_renderbuffer_gtt() is idempotent, the double mapping did
not cause bugs for depthstencil buffers *without* separate stencil).
2. Stop overriding gl_framebuffer::_DepthBuffer,_StencilBuffer
Normally, if a depthstencil buffer is attached to the framebuffer's
depth attachment point, then _mesa_update_framebuffer() installs
a wrapper depth renderbuffer at gl_framebuffer::_DepthBuffer. Ditto for
the stencil attachment point and gl_framebuffer::_StencilBuffer
A depthstencil intel_renderbuffer with separate stencil contains hidden
depth and stencil renderbuffers, which are the *real* renderbuffers. In
order to force swrast to work, we were installing, in
brw_update_draw_buffer(), the hidden renderbuffers at
gl_framebuffer::_DepthBuffer and _StencilBuffer, thus overriding the
behavior of _mesa_update_framebuffer(). However, now that
intel_renderbuffer_map() is implemented with MapRenderbuffer(),
overriding _mesa_update_framebuffer's introduces bugs. This patch
removes the override code.
Fixes several Piglit tests on gen7.
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d2235e6c76a8a6aef2a14ca57c68403cf056921
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Wed Nov 16 22:10:11 2011 -0800
intel: Don't use special stencil span accessors
The special stencil span accessors, as set by intel_span_init_funcs.
perform software W detiling. Since intel_renderbuffer_map() now uses
MapRenderbuffer, rb->Data points to an *untiled* stencil buffer.
Fixes several Piglit tests on gen7.
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=16f2e7e0fb1213b09c8c355ac3c67e25c9ab34ca
Author: Ben Skeggs <bskeggs at redhat.com>
Date: Thu Nov 17 10:17:06 2011 +1000
nvc0: add support for GF119 (NVD9)
Signed-off-by: Ben Skeggs <bskeggs at redhat.com>
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