Mesa (master): r600g: uarl fixes.
Dave Airlie
airlied at kemper.freedesktop.org
Sun Oct 9 15:49:00 UTC 2011
Module: Mesa
Branch: master
Commit: 9b34cea7e91f90023ca3490603155d758cbdee1c
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b34cea7e91f90023ca3490603155d758cbdee1c
Author: Dave Airlie <airlied at redhat.com>
Date: Sun Sep 25 15:41:59 2011 +0100
r600g: uarl fixes.
Not 100% sure these are correct yet
---
src/gallium/drivers/r600/r600_asm.c | 3 ++
src/gallium/drivers/r600/r600_shader.c | 58 ++++++++++++++++++++++----------
2 files changed, 43 insertions(+), 18 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index 663e41f..597be69 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -55,7 +55,10 @@ static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 1280355..b385524 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1036,7 +1036,7 @@ static int tgsi_int_to_flt(struct r600_shader_ctx *ctx)
return 0;
}
-static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
+static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
{
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
struct r600_bytecode_alu alu;
@@ -1070,7 +1070,7 @@ static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
default:
break;
}
- if (i == lasti) {
+ if (i == lasti || trans_only) {
alu.last = 1;
}
r = r600_bytecode_add_alu(ctx->bc, &alu);
@@ -1082,12 +1082,17 @@ static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
static int tgsi_op2(struct r600_shader_ctx *ctx)
{
- return tgsi_op2_s(ctx, 0);
+ return tgsi_op2_s(ctx, 0, 0);
}
static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
{
- return tgsi_op2_s(ctx, 1);
+ return tgsi_op2_s(ctx, 1, 0);
+}
+
+static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
+{
+ return tgsi_op2_s(ctx, 0, 1);
}
static int tgsi_ineg(struct r600_shader_ctx *ctx)
@@ -2912,18 +2917,22 @@ static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
case TGSI_OPCODE_ARR:
alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
break;
+ case TGSI_OPCODE_UARL:
+ break;
default:
assert(0);
return -1;
}
- r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
- alu.last = 1;
- alu.dst.sel = ctx->ar_reg;
- alu.dst.write = 1;
- r = r600_bytecode_add_alu(ctx->bc, &alu);
- if (r)
- return r;
+ if (alu.inst) {
+ r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
+ alu.last = 1;
+ alu.dst.sel = ctx->ar_reg;
+ alu.dst.write = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
/* TODO: Note that the MOVA can be avoided if we never use AR for
* indexing non-CB registers in the current ALU clause. Similarly, we
@@ -2933,8 +2942,12 @@ static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
* has been modified in each clause. */
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT;
- alu.src[0].sel = ctx->ar_reg;
- alu.src[0].chan = 0;
+ if (inst->Instruction.Opcode == TGSI_OPCODE_UARL)
+ r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
+ else {
+ alu.src[0].sel = ctx->ar_reg;
+ alu.src[0].chan = 0;
+ }
alu.last = 1;
r = r600_bytecode_add_alu(ctx->bc, &alu);
if (r)
@@ -2981,6 +2994,8 @@ static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
return r;
break;
+ case TGSI_OPCODE_UARL:
+ break;
default:
assert(0);
return -1;
@@ -2988,7 +3003,10 @@ static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
memset(&alu, 0, sizeof(alu));
alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT;
- alu.src[0].sel = ctx->ar_reg;
+ if (inst->Instruction.Opcode == TGSI_OPCODE_UARL)
+ r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
+ else
+ alu.src[0].sel = ctx->ar_reg;
alu.last = 1;
r = r600_bytecode_add_alu(ctx->bc, &alu);
@@ -3355,9 +3373,7 @@ static int tgsi_umad(struct r600_shader_ctx *ctx)
r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
}
- if (i == lasti) {
- alu.last = 1;
- }
+ alu.last = 1;
r = r600_bytecode_add_alu(ctx->bc, &alu);
if (r)
return r;
@@ -3560,6 +3576,8 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
{TGSI_OPCODE_RESINFO, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
+ {TGSI_OPCODE_UARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_r600_arl},
+ {TGSI_OPCODE_UCMP, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
};
@@ -3708,7 +3726,7 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
{TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT, tgsi_op2},
{TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT, tgsi_op2},
{TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
- {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT, tgsi_op2},
+ {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT, tgsi_op2_trans},
{TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT, tgsi_op2},
{TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT, tgsi_op2},
{TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
@@ -3730,6 +3748,8 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
{TGSI_OPCODE_RESINFO, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
+ {TGSI_OPCODE_UARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_eg_arl},
+ {TGSI_OPCODE_UCMP, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
};
@@ -3900,5 +3920,7 @@ static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
{TGSI_OPCODE_RESINFO, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
+ {TGSI_OPCODE_UARL, 0, 0, tgsi_unsupported},
+ {TGSI_OPCODE_UCMP, 0, 0, tgsi_unsupported},
{TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
};
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