Mesa (master): i965: Rename pixel_scoreboard_clear to last_render_target for clarity.
Kenneth Graunke
kwg at kemper.freedesktop.org
Tue Oct 18 22:57:12 UTC 2011
Module: Mesa
Branch: master
Commit: 53798f90e818e9bf213c3ae4298751362a5ecd50
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=53798f90e818e9bf213c3ae4298751362a5ecd50
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Oct 7 22:26:40 2011 -0700
i965: Rename pixel_scoreboard_clear to last_render_target for clarity.
Finding this bit in the documentation proved challenging. It wasn't in
the SEND instruction's message descriptor section, nor the data port
message descriptor section. It turns out to be part of the Render
Target Write message's control bits, and in the documentation is named
"Last Render Target Select".
Shaders that use Multiple Render Targets should set this bit on the last
RT write, but not on any prior ones.
The GPU does update the Pixel Scoreboard appropriately, but doesn't
document this bit as directly causing a scoreboard clear.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
---
src/mesa/drivers/dri/i965/brw_disasm.c | 2 +-
src/mesa/drivers/dri/i965/brw_eu.h | 2 +-
src/mesa/drivers/dri/i965/brw_eu_emit.c | 18 +++++++++---------
src/mesa/drivers/dri/i965/brw_structs.h | 8 ++++----
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp | 2 +-
5 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c
index a010cd7..1dd6b4b 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -1036,7 +1036,7 @@ int brw_disasm (FILE *file, struct brw_instruction *inst, int gen)
} else {
format (file, " (%d, %d, %d, %d)",
inst->bits3.dp_write.binding_table_index,
- (inst->bits3.dp_write.pixel_scoreboard_clear << 3) |
+ (inst->bits3.dp_write.last_render_target << 3) |
inst->bits3.dp_write.msg_control,
inst->bits3.dp_write.msg_type,
inst->bits3.dp_write.send_commit_msg);
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 2f353b9..33492f6 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -881,7 +881,7 @@ void brw_set_dp_write_message(struct brw_compile *p,
GLuint msg_type,
GLuint msg_length,
bool header_present,
- GLuint pixel_scoreboard_clear,
+ GLuint last_render_target,
GLuint response_length,
GLuint end_of_thread,
GLuint send_commit_msg);
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 078e289..5574df8 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -537,7 +537,7 @@ brw_set_dp_write_message(struct brw_compile *p,
GLuint msg_type,
GLuint msg_length,
bool header_present,
- GLuint pixel_scoreboard_clear,
+ GLuint last_render_target,
GLuint response_length,
GLuint end_of_thread,
GLuint send_commit_msg)
@@ -565,24 +565,24 @@ brw_set_dp_write_message(struct brw_compile *p,
if (intel->gen >= 7) {
insn->bits3.gen7_dp.binding_table_index = binding_table_index;
insn->bits3.gen7_dp.msg_control = msg_control;
- insn->bits3.gen7_dp.pixel_scoreboard_clear = pixel_scoreboard_clear;
+ insn->bits3.gen7_dp.last_render_target = last_render_target;
insn->bits3.gen7_dp.msg_type = msg_type;
} else if (intel->gen == 6) {
insn->bits3.gen6_dp.binding_table_index = binding_table_index;
insn->bits3.gen6_dp.msg_control = msg_control;
- insn->bits3.gen6_dp.pixel_scoreboard_clear = pixel_scoreboard_clear;
+ insn->bits3.gen6_dp.last_render_target = last_render_target;
insn->bits3.gen6_dp.msg_type = msg_type;
insn->bits3.gen6_dp.send_commit_msg = send_commit_msg;
} else if (intel->gen == 5) {
insn->bits3.dp_write_gen5.binding_table_index = binding_table_index;
insn->bits3.dp_write_gen5.msg_control = msg_control;
- insn->bits3.dp_write_gen5.pixel_scoreboard_clear = pixel_scoreboard_clear;
+ insn->bits3.dp_write_gen5.last_render_target = last_render_target;
insn->bits3.dp_write_gen5.msg_type = msg_type;
insn->bits3.dp_write_gen5.send_commit_msg = send_commit_msg;
} else {
insn->bits3.dp_write.binding_table_index = binding_table_index;
insn->bits3.dp_write.msg_control = msg_control;
- insn->bits3.dp_write.pixel_scoreboard_clear = pixel_scoreboard_clear;
+ insn->bits3.dp_write.last_render_target = last_render_target;
insn->bits3.dp_write.msg_type = msg_type;
insn->bits3.dp_write.send_commit_msg = send_commit_msg;
}
@@ -619,12 +619,12 @@ brw_set_dp_read_message(struct brw_compile *p,
if (intel->gen >= 7) {
insn->bits3.gen7_dp.binding_table_index = binding_table_index;
insn->bits3.gen7_dp.msg_control = msg_control;
- insn->bits3.gen7_dp.pixel_scoreboard_clear = 0;
+ insn->bits3.gen7_dp.last_render_target = 0;
insn->bits3.gen7_dp.msg_type = msg_type;
} else if (intel->gen == 6) {
insn->bits3.gen6_dp.binding_table_index = binding_table_index;
insn->bits3.gen6_dp.msg_control = msg_control;
- insn->bits3.gen6_dp.pixel_scoreboard_clear = 0;
+ insn->bits3.gen6_dp.last_render_target = 0;
insn->bits3.gen6_dp.msg_type = msg_type;
insn->bits3.gen6_dp.send_commit_msg = 0;
} else if (intel->gen == 5) {
@@ -1714,7 +1714,7 @@ void brw_oword_block_write_scratch(struct brw_compile *p,
msg_type,
mlen,
true, /* header_present */
- 0, /* pixel scoreboard */
+ 0, /* not a render target */
send_commit_msg, /* response_length */
0, /* eot */
send_commit_msg);
@@ -2059,7 +2059,7 @@ void brw_fb_WRITE(struct brw_compile *p,
msg_type,
msg_length,
header_present,
- 1, /* pixel scoreboard */
+ 1, /* last render target write */
response_length,
eot,
0 /* send_commit_msg */);
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index b47be69..af83511 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -1314,7 +1314,7 @@ struct brw_instruction
struct {
GLuint binding_table_index:8;
GLuint msg_control:3;
- GLuint pixel_scoreboard_clear:1;
+ GLuint last_render_target:1;
GLuint msg_type:3;
GLuint send_commit_msg:1;
GLuint response_length:4;
@@ -1327,7 +1327,7 @@ struct brw_instruction
struct {
GLuint binding_table_index:8;
GLuint msg_control:3;
- GLuint pixel_scoreboard_clear:1;
+ GLuint last_render_target:1;
GLuint msg_type:3;
GLuint send_commit_msg:1;
GLuint pad0:3;
@@ -1355,7 +1355,7 @@ struct brw_instruction
GLuint binding_table_index:8;
GLuint msg_control:3;
GLuint slot_group_select:1;
- GLuint pixel_scoreboard_clear:1;
+ GLuint last_render_target:1;
GLuint msg_type:4;
GLuint send_commit_msg:1;
GLuint pad0:1;
@@ -1371,7 +1371,7 @@ struct brw_instruction
GLuint binding_table_index:8;
GLuint msg_control:3;
GLuint slot_group_select:1;
- GLuint pixel_scoreboard_clear:1;
+ GLuint last_render_target:1;
GLuint pad0:1;
GLuint msg_type:4;
GLuint pad1:1;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index e93e319..73898b7 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -492,7 +492,7 @@ vec4_visitor::generate_scratch_write(vec4_instruction *inst,
msg_type,
3, /* mlen */
true, /* header present */
- false, /* pixel scoreboard */
+ false, /* not a render target write */
write_commit, /* rlen */
false, /* eot */
write_commit);
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