Mesa (master): i965/vs: Fix point size handling on gen4.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 9bd8d90646572a170bd96a72d2f8d5739df381be
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9bd8d90646572a170bd96a72d2f8d5739df381be

Author: Eric Anholt <eric at anholt.net>
Date:   Tue Aug 30 15:34:43 2011 -0700

i965/vs: Fix point size handling on gen4.

Fixes glsl-vs-point-size.

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

---

 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index e0e3ce3..dac8cf9 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -1748,14 +1748,15 @@ vec4_visitor::emit_psiz_and_flags(struct brw_reg reg)
       emit(MOV(header1, 0u));
 
       if (c->prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_PSIZ)) {
-	 assert(!"finishme: psiz");
-	 src_reg psiz;
+	 src_reg psiz = src_reg(output_reg[VERT_RESULT_PSIZ]);
 
+	 current_annotation = "Point size";
 	 header1.writemask = WRITEMASK_W;
-	 emit(MUL(header1, psiz, 1u << 11));
+	 emit(MUL(header1, psiz, src_reg((float)(1 << 11))));
 	 emit(AND(header1, src_reg(header1), 0x7ff << 8));
       }
 
+      current_annotation = "Clipping flags";
       for (i = 0; i < c->key.nr_userclip; i++) {
 	 vec4_instruction *inst;
 
@@ -1792,7 +1793,7 @@ vec4_visitor::emit_psiz_and_flags(struct brw_reg reg)
       }
 
       header1.writemask = WRITEMASK_XYZW;
-      emit(MOV(reg, src_reg(header1)));
+      emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), src_reg(header1)));
    } else if (intel->gen < 6) {
       emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), 0u));
    } else {