Mesa (master): radeon/llvm: fix fp immediates on SI
Christian König
deathsimple at kemper.freedesktop.org
Thu Aug 2 13:15:46 UTC 2012
Module: Mesa
Branch: master
Commit: a3c6607be19af895ed6857c0a82b9b0821893dc6
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a3c6607be19af895ed6857c0a82b9b0821893dc6
Author: Christian König <deathsimple at vodafone.de>
Date: Wed Aug 1 20:46:39 2012 +0200
radeon/llvm: fix fp immediates on SI
I don't know if this is a good idea, but it
fixes the problem at hand.
Signed-off-by: Christian König <deathsimple at vodafone.de>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
---
src/gallium/drivers/radeon/SICodeEmitter.cpp | 27 +++++++++++++++++++------
1 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/radeon/SICodeEmitter.cpp b/src/gallium/drivers/radeon/SICodeEmitter.cpp
index 9fc4aab..fae56f4 100644
--- a/src/gallium/drivers/radeon/SICodeEmitter.cpp
+++ b/src/gallium/drivers/radeon/SICodeEmitter.cpp
@@ -232,7 +232,7 @@ uint64_t SICodeEmitter::getMachineOpValue(const MachineInstr &MI,
case MachineOperand::MO_FPImmediate:
// XXX: Not all instructions can use inline literals
// XXX: We should make sure this is a 32-bit constant
- return LITERAL_REG | (MO.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue() << 32);
+ return LITERAL_REG;
case MachineOperand::MO_MachineBasicBlock:
return (*BBIndexes.find(MI.getParent()->getNumber())).second -
@@ -321,13 +321,26 @@ uint64_t SICodeEmitter::VOPPostEncode(const MachineInstr &MI,
// Add one to skip over the destination reg operand.
for (unsigned opIdx = 1; opIdx < numSrcOps + 1; opIdx++) {
- if (!MI.getOperand(opIdx).isReg()) {
+ const MachineOperand &MO = MI.getOperand(opIdx);
+ switch(MO.getType()) {
+ case MachineOperand::MO_Register:
+ {
+ unsigned reg = MI.getOperand(opIdx).getReg();
+ if (AMDGPU::VReg_32RegClass.contains(reg)
+ || AMDGPU::VReg_64RegClass.contains(reg)) {
+ Value |= (VGPR_BIT(opIdx)) << vgprBitOffset;
+ }
+ }
+ break;
+
+ case MachineOperand::MO_FPImmediate:
+ // XXX: Not all instructions can use inline literals
+ // XXX: We should make sure this is a 32-bit constant
+ Value |= (MO.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue() << 32);
continue;
- }
- unsigned reg = MI.getOperand(opIdx).getReg();
- if (AMDGPU::VReg_32RegClass.contains(reg)
- || AMDGPU::VReg_64RegClass.contains(reg)) {
- Value |= (VGPR_BIT(opIdx)) << vgprBitOffset;
+
+ default:
+ break;
}
}
return Value;
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