Mesa (master): radeon/llvm: Add support for fneg on SI
Tom Stellard
tstellar at kemper.freedesktop.org
Thu Aug 2 20:39:30 UTC 2012
Module: Mesa
Branch: master
Commit: a35eea786823f0130b925cb25486d7d162f2d68c
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a35eea786823f0130b925cb25486d7d162f2d68c
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Thu Aug 2 14:05:20 2012 -0400
radeon/llvm: Add support for fneg on SI
---
src/gallium/drivers/radeon/SIISelLowering.cpp | 15 +++++++++++++++
src/gallium/drivers/radeon/SIInstructions.td | 1 +
2 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/radeon/SIISelLowering.cpp b/src/gallium/drivers/radeon/SIISelLowering.cpp
index a14cb6f..3e08e88 100644
--- a/src/gallium/drivers/radeon/SIISelLowering.cpp
+++ b/src/gallium/drivers/radeon/SIISelLowering.cpp
@@ -99,6 +99,21 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
MI->eraseFromParent();
break;
+ case AMDGPU::FNEG_SI:
+ BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64))
+ .addOperand(MI->getOperand(0))
+ .addOperand(MI->getOperand(1))
+ // VSRC1-2 are unused, but we still need to fill all the
+ // operand slots, so we just reuse the VSRC0 operand
+ .addOperand(MI->getOperand(1))
+ .addOperand(MI->getOperand(1))
+ .addImm(0) // ABS
+ .addImm(0) // CLAMP
+ .addImm(0) // OMOD
+ .addImm(1); // NEG
+ MI->eraseFromParent();
+ break;
+
case AMDGPU::SI_INTERP:
LowerSI_INTERP(MI, *BB, I, MRI);
break;
diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td
index 1f03ea5..c753943 100644
--- a/src/gallium/drivers/radeon/SIInstructions.td
+++ b/src/gallium/drivers/radeon/SIInstructions.td
@@ -1017,6 +1017,7 @@ def : Pat <
def CLAMP_SI : CLAMP<VReg_32>;
def FABS_SI : FABS<VReg_32>;
+def FNEG_SI : FNEG<VReg_32>;
def : Extract_Element <f32, v4f32, VReg_128, 0, sel_x>;
def : Extract_Element <f32, v4f32, VReg_128, 1, sel_y>;
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