Mesa (master): i965: Emit a CS stall before timestamp writes.
Kenneth Graunke
kwg at kemper.freedesktop.org
Wed Aug 8 16:34:46 UTC 2012
Module: Mesa
Branch: master
Commit: a2cdd5ada8ae315acbc4225398b7cbf78181f610
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a2cdd5ada8ae315acbc4225398b7cbf78181f610
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Aug 7 09:32:46 2012 -0700
i965: Emit a CS stall before timestamp writes.
This implements one of the Sandybridge PIPE_CONTROL workarounds. It
doesn't appear to be required for Ivybridge.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Eric Anholt <eric at anholt.net>
---
src/mesa/drivers/dri/i965/brw_queryobj.c | 14 ++++++++++++++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c
index afa3091..cbe67ad 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -49,6 +49,20 @@ static void
write_timestamp(struct intel_context *intel, drm_intel_bo *query_bo, int idx)
{
if (intel->gen >= 6) {
+ /* Emit workaround flushes: */
+ if (intel->gen == 6) {
+ /* The timestamp write below is a non-zero post-sync op, which on
+ * Gen6 necessitates a CS stall. CS stalls need stall at scoreboard
+ * set. See the comments for intel_emit_post_sync_nonzero_flush().
+ */
+ BEGIN_BATCH(4);
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
+ OUT_BATCH(PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+ }
+
BEGIN_BATCH(5);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
OUT_BATCH(PIPE_CONTROL_WRITE_TIMESTAMP);
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