Mesa (master): i965: Add performance debug for fast clear fallbacks.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: b4da272a6ea58a7c81c71477d65d82651555709a
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b4da272a6ea58a7c81c71477d65d82651555709a

Author: Eric Anholt <eric at anholt.net>
Date:   Thu Jul 12 13:14:42 2012 -0700

i965: Add performance debug for fast clear fallbacks.

Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

---

 src/mesa/drivers/dri/i965/brw_clear.c |   10 +++++++++-
 1 files changed, 9 insertions(+), 1 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index 05dd68b..e56a26a 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -107,14 +107,22 @@ brw_fast_clear_depth(struct gl_context *ctx)
     * a previous clear had happened at a different clear value and resolve it
     * first.
     */
-   if (ctx->Scissor.Enabled)
+   if (ctx->Scissor.Enabled) {
+      perf_debug("Failed to fast clear depth due to scissor being enabled.  "
+                 "Possible 5%% performance win if avoided.\n");
       return false;
+   }
 
    /* The rendered area has to be 8x4 samples, not resolved pixels, so we look
     * at the miptree slice dimensions instead of renderbuffer size.
     */
    if (mt->level[depth_irb->mt_level].width % 8 != 0 ||
        mt->level[depth_irb->mt_level].height % 4 != 0) {
+      perf_debug("Failed to fast clear depth due to width/height %d,%d not "
+                 "being aligned to 8,4.  Possible 5%% performance win if "
+                 "avoided\n",
+                 mt->level[depth_irb->mt_level].width,
+                 mt->level[depth_irb->mt_level].height);
       return false;
    }