Mesa (master): radeon/llvm: Lower store_output intrinsic during DAG lowering

[Tom Stellard]

Module: Mesa
Branch: master
Commit: f3480f92349c90f55e2e80d9a4536ab048fb5652
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f3480f92349c90f55e2e80d9a4536ab048fb5652

Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Thu Jul 26 17:10:47 2012 +0000

radeon/llvm: Lower store_output intrinsic during DAG lowering

---

 src/gallium/drivers/radeon/AMDGPUIntrinsics.td  |    2 +-
 src/gallium/drivers/radeon/R600ISelLowering.cpp |   35 +++++++++++++---------
 src/gallium/drivers/radeon/R600Instructions.td  |    7 ----
 3 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/src/gallium/drivers/radeon/AMDGPUIntrinsics.td b/src/gallium/drivers/radeon/AMDGPUIntrinsics.td
index 78f072c..89cc7e1 100644
--- a/src/gallium/drivers/radeon/AMDGPUIntrinsics.td
+++ b/src/gallium/drivers/radeon/AMDGPUIntrinsics.td
@@ -16,7 +16,7 @@ let TargetPrefix = "AMDGPU", isTarget = 1 in {
   def int_AMDGPU_load_const : Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;
   def int_AMDGPU_load_imm : Intrinsic<[llvm_v4f32_ty], [llvm_i32_ty], [IntrNoMem]>;
   def int_AMDGPU_reserve_reg : Intrinsic<[], [llvm_i32_ty], [IntrNoMem]>;
-  def int_AMDGPU_store_output : Intrinsic<[], [llvm_float_ty, llvm_i32_ty], [IntrNoMem]>;
+  def int_AMDGPU_store_output : Intrinsic<[], [llvm_float_ty, llvm_i32_ty], []>;
   def int_AMDGPU_swizzle : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty], [IntrNoMem]>;
 
   def int_AMDGPU_arl : Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index 7f79359..4f2bfe3 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -37,6 +37,8 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
 
   setOperationAction(ISD::FSUB, MVT::f32, Expand);
 
+  setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
+
   setOperationAction(ISD::ROTL, MVT::i32, Custom);
 
   setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
@@ -175,20 +177,6 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
       break;
     }
 
-  case AMDGPU::STORE_OUTPUT:
-    {
-      int64_t OutputIndex = MI->getOperand(1).getImm();
-      unsigned OutputReg = AMDGPU::R600_TReg32RegClass.getRegister(OutputIndex);
-
-      BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::COPY), OutputReg)
-                  .addOperand(MI->getOperand(0));
-
-      if (!MRI.isLiveOut(OutputReg)) {
-        MRI.addLiveOut(OutputReg);
-      }
-      break;
-    }
-
   case AMDGPU::RESERVE_REG:
     {
       R600MachineFunctionInfo * MFI = MF->getInfo<R600MachineFunctionInfo>();
@@ -285,6 +273,25 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
   case ISD::ROTL: return LowerROTL(Op, DAG);
   case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
   case ISD::SETCC: return LowerSETCC(Op, DAG);
+  case ISD::INTRINSIC_VOID: {
+    SDValue Chain = Op.getOperand(0);
+    unsigned IntrinsicID =
+                         cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
+    switch (IntrinsicID) {
+    case AMDGPUIntrinsic::AMDGPU_store_output: {
+      MachineFunction &MF = DAG.getMachineFunction();
+      MachineRegisterInfo &MRI = MF.getRegInfo();
+      int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
+      unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
+      if (!MRI.isLiveOut(Reg)) {
+        MRI.addLiveOut(Reg);
+      }
+      return DAG.getCopyToReg(Chain, Op.getDebugLoc(), Reg, Op.getOperand(2));
+    }
+    default: return SDValue();
+    }
+    break;
+  }
   }
 }
 
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index bb65c17..57bb6cb 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -1152,13 +1152,6 @@ def RESERVE_REG : AMDGPUShaderInst <
   [(int_AMDGPU_reserve_reg imm:$src)]
 >;
 
-def STORE_OUTPUT: AMDGPUShaderInst <
-  (outs),
-  (ins R600_Reg32:$src0, i32imm:$src1),
-  "STORE_OUTPUT $src0, $src1",
-  [(int_AMDGPU_store_output R600_Reg32:$src0, imm:$src1)]
->;
-
 def TXD: AMDGPUShaderInst <
   (outs R600_Reg128:$dst),
   (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),